The BRS-100-GW1NR9 is a cheap, scripted-workflow, FPGA dev board. Ships with an example project so your projects can hit the ground running!
In this article we will see how we can use the Vitis Functional Simulation feature to simulate a Versal AI Engine application from MATLAB
In this article we will see how we can use the Vitis Functional Simulation feature to simulate a Versal AI Engine application from Python
Compile a FreeRTOS HelloWorld for the Zynq MPSoC FPGA targetting the R5 dual core CPU set up in lock-step mode and test the error injection.
BMP180 I2C sensor integration with KR260 using MicroBlaze V with Vitis/VIVADO 2025.1 tool for temperature/pressure & altitude information.
Design, test and deploy various FIR filters on FPGA with the MYIR development board
Functionally verifying a Vitis HLS Kernel using Python.
In this tutorial we are using Python to generate input text file to feed the AI Engine simulator to test our FFT
This project implements a hardware-based True Random Number Generator (TRNG)
In this tutorial, I am showing how to build a 1024 point FFT on the AMD AIE-ML using the DSP Library which is available as Open Source
This project is the begin of a series about KRS Unleashed, a revised version of the original KRS.
This project is part of a series about KRS Unleashed, a revised version of the original KRS. This article walks through the on-board setup.
This project is part of a series about KRS Unleashed, a revised version of the original KRS. This article walks through the OS workspace.
This project is part of a series about KRS Unleashed, a revised version of the original KRS. This article walks through the Vitis workspace.
Hardware and software design for LED control using a custom AXI IP in Vivado 2023.2 and Vitis Unified 2023.2 (using Kria KD240)
Edge AI meets deterministic motion — the CM5 sees a face, the FPGA makes it wave. Real-time robotics on the Tile Carrier Card
Base Vivado project to configure the PS on the MYIR MYD-CZU3EG development board as a base for software and Linux development
This tutorial is discussing about how I debugged an issue related to memory alignment in AIE-ML
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.2 flow for Avnet Vitis 2020.1 platforms.
This guide provides detailed instructions for targeting the DNNDK samples from the Xilinx Vitis-AI 1.1 flow for Avnet Vitis 2019.2 platforms
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.3 flow for Avnet Vitis 2020.2 platforms.
Great introduction to MIPI CSI2. Lattice Crosslink FPGA is programmed to imitate an IMX219 image sensor and transmit images to Jetson Nano.
Leveraging HLS functions to create a image processing solution which implements edge detection (Sobel) in programmable logic.
This project walks through the basics of software defined radio using GNU Radio with Ettus' new B206mini USRP.
