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Introduction
ML Project Design
Read moreRecently, I was invited to an industry event that included a demo night. Keen to showcase some of my products, I decided to create a demo based on the Embedded System Tile, which features an AMD Spartan-7 FPGA mounted on the Tile Carrier Card. In addition to hosting the Embedded System Tile, the Tile Carrier Card also includes a Raspberry Pi Compute Module 5. We have previously examined the bring-up process for the Tile Carrier Card here.
In this project, I want to create something that demonstrates the flexibility of the solution for prototyping. To achieve this, I plan for the Raspberry Pi CM5 to run a face detection algorithm. When a face is detected, a robot arm connected to the Tile Carrier Card’s Pmods will perform a simple wave to say hello.
This robot arm will be controlled and commanded by the FPGA on the Embedded System Tile. Communication between the Raspberry Pi CM5 and the Embedded System Tile will take place over a UART link.
Why use the Embedded System Tile?Apart from the fact that I am an FPGA engineer and wanted to include the Embedded System Tile in this project, the Raspberry Pi CM5 does not have enough hardware PWM outputs. The RPi CM5 can only provide four hardware PWM outputs, while the robot arm requires at least six. Although the RPi CM5 can generate software-based PWM signals, this approach is not well suited for robotics, as it suffers from jitter.
It is also important to note that the robot arm used in this application is quite simple. An arm used in a more professional solution would employ a more sophisticated motor drive system. These advanced drive systems, such as Space Vector Modulation (SVM) are best implemented using an FPGA.
ConfigurationThis project needs the following elements.
- Tile Carrier Card fitted with the Embedded System Tile and RPi CM5.
- HDMI Monitor connected to the Tile Carrier Card.
- USB Mouse / Keyboard Tile Carrier Card.
- USB Web Cam connected to Tile Carrier Card.
- Robot Arm Connected to the Tile Carrier Card using Pmod Interfaces.
The FPGA design is derived from a framework we have used several times before. In this project, we will utilize the UART-to-AXI protocol framework, which allows a sequence of bytes sent over the UART interface to be converted into an AXI write transaction.
As a pure RTL design, the system includes the following functions:
- AXI Stream UART.
- AXI Protocol - UART to AXI conversion.
- AXI Register - Breaks out a number of registers - we need 6 for the robot arm one for each of the joints.
- Pulse Width Modulation - set to 50 HZ duty cycle.
The architecture of the RTL design is:
The RTL Code for the design can be seen here
UART
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.adiuvo_uart.all;
entity uart is generic (
reset_level : std_logic := '0'; -- reset level which causes a reset
clk_freq : natural := 100_000_000; -- oscillator frequency
baud_rate : natural := 115200 -- baud rate
);
port (
--!System Inputs
clk : in std_logic;
reset : in std_logic;
--!External Interfaces
rx : in std_logic;
tx : out std_logic;
--! Master AXIS Interface
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
--! Slave AXIS Interface
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tvalid : in std_logic
);
end entity;
architecture rtl of uart is
constant bit_period : integer := (clk_freq/baud_rate) - 1;
type cntrl_fsm is (idle, set_tx,wait_tx);
type rx_fsm is (idle, start, sample, check, wait_axis);
signal current_state : cntrl_fsm; --:= idle;
signal rx_state : rx_fsm;-- := idle;
signal baud_counter : unsigned(vector_size(real(clk_freq), real(baud_rate)) downto 0) := (others => '0'); --timer for outgoing signals
signal baud_en : std_logic := '0';
signal meta_reg : std_logic_vector(3 downto 0) := (others => '0'); -- fe detection too
signal capture : std_logic_vector(7 downto 0) := (others => '0'); -- data and parity
signal bit_count : integer range 0 to 1023 := 0;
signal pos_count : integer range 0 to 15 := 0;
signal running : std_logic := '0';
signal load_tx : std_logic := '0';
signal complete : std_logic := '0';
signal tx_reg : std_logic_vector(11 downto 0) := (others => '0');
signal tmr_reg : std_logic_vector(11 downto 0) := (others => '0');
signal payload : std_logic_vector(7 downto 0) := (others => '0');
constant zero : std_logic_vector(tmr_reg'range) := (others => '0');
begin
process (reset, clk)
begin
if reset = reset_level then
current_state <= idle;
payload <= (others => '0');
load_tx <= '0';
elsif rising_edge(clk) then
load_tx <= '0';
case current_state is
when idle =>
if s_axis_tvalid = '1' then
current_state <= set_tx;
load_tx <= '1';
payload <= s_axis_tdata;
end if;
when set_tx =>
current_state <= wait_tx;
when wait_tx =>
if complete = '1' then
current_state <= idle;
end if;
when others =>
current_state <= idle;
end case;
end if;
end process;
s_axis_tready <= '1' when (current_state = idle) else '0';
process (reset, clk)
--! baud counter for output TX
begin
if reset = reset_level then
baud_counter <= (others => '0');
baud_en <= '0';
elsif rising_edge(clk) then
baud_en <= '0';
if (load_tx = '1') then
baud_counter <= (others => '0');
elsif (baud_counter = bit_period) then
baud_en <= '1';
baud_counter <= (others => '0');
else
baud_counter <= baud_counter + 1;
end if;
end if;
end process;
process (reset, clk)
--!metastability protection rx signal
begin
if reset = reset_level then
meta_reg <= (others => '1');
elsif rising_edge(clk) then
meta_reg <= meta_reg(meta_reg'high - 1 downto meta_reg'low) & rx;
end if;
end process;
process (reset, clk)
begin
if reset = reset_level then
pos_count <= 0;
bit_count <= 0;
capture <= (others => '0');
rx_state <= idle;
m_axis_tvalid <= '0';
m_axis_tdata <= (others => '0');
elsif rising_edge(clk) then
case rx_state is
when idle =>
m_axis_tvalid <= '0';
if meta_reg(meta_reg'high downto meta_reg'high - 1) = fe_det then
pos_count <= 0;
bit_count <= 0;
capture <= (others => '0');
rx_state <= start;
end if;
when start =>
if bit_count = bit_period then
bit_count <= 0;
rx_state <= sample;
else
bit_count <= bit_count + 1;
end if;
when sample =>
bit_count <= bit_count + 1;
rx_state <= sample;
if bit_count = (bit_period/2) and (pos_count < 8) then
capture <= meta_reg(meta_reg'high) & capture(capture'high downto capture'low + 1);
elsif bit_count = bit_period then
if pos_count = 8 then
rx_state <= check;
else
pos_count <= pos_count + 1;
bit_count <= 0;
end if;
end if;
when check =>
if parity(capture) = '1' then
m_axis_tvalid <= '1';
m_axis_tdata <= capture(7 downto 0);
rx_state <= wait_axis;
else
m_axis_tvalid <= '1';
m_axis_tdata <= capture(7 downto 0);
rx_state <= wait_axis;
end if;
when wait_axis =>
if m_axis_tready = '1' then
m_axis_tvalid <= '0';
rx_state <= idle;
end if;
end case;
end if;
end process;
op_uart : process (reset, clk)
begin
if reset = reset_level then
tx_reg <= (others => '1');
tmr_reg <= (others => '0');
elsif rising_edge(clk) then
if load_tx = '1' then
tx_reg <= stop_bit & not(parity(payload)) & payload & start_bit ;
tmr_reg <= (others => '1');
elsif baud_en = '1' then
tx_reg <= '1' & tx_reg(tx_reg'high downto tx_reg'low + 1);
tmr_reg <= tmr_reg(tmr_reg'high - 1 downto tmr_reg'low) & '0';
end if;
end if;
end process;
tx <= tx_reg(tx_reg'low);
complete <= '1' when (tmr_reg = zero and current_state = wait_tx) else '0';
end architecture;UART PKG
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package adiuvo_uart is
function vector_size(clk_freq, baud_rate : real) return integer;
function parity (a : std_logic_vector) return std_logic;
constant fe_det : std_logic_vector(1 downto 0) := "10";
constant start_bit : std_logic := '0';
constant stop_bit : std_logic_vector := "11";
end package;
package body adiuvo_uart is
function vector_size(clk_freq, baud_rate : real) return integer is
variable div : real;
variable res : real;
begin
div := (clk_freq/baud_rate);
res := CEIL(LOG(div)/LOG(2.0));
return integer(res - 1.0);
end;
function parity (a : std_logic_vector) return std_logic is
variable y : std_logic := '0';
begin
for i in a'range loop
y := y xor a(i);
end loop;
return y;
end parity;
end package body adiuvo_uart;Protocol
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Declare entity
entity axi_protocol is
generic(
G_AXIL_DATA_WIDTH :integer := 32; --Width of AXI Lite data bus
G_AXI_ADDR_WIDTH :integer := 32; --Width of AXI Lite Address Bu
G_AXI_ID_WIDTH :integer := 8; --Width of AXI ID Bus
G_AXI_AWUSER_WIDTH :integer := 1 --Width of AXI AW User bus
);
port(
--Master clock & reset
clk :in std_ulogic; --System clock
reset :in std_ulogic; --System reset, async active low
--! Master AXIS Interface
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
--! Slave AXIS Interface
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tvalid : in std_logic;
--! AXIL Interface
--!Write address
axi_awaddr : out std_logic_vector(G_AXI_ADDR_WIDTH-1 downto 0);
axi_awprot : out std_logic_vector(2 downto 0);
axi_awvalid : out std_logic;
--!write data
axi_wdata : out std_logic_vector(G_AXIL_DATA_WIDTH-1 downto 0);
axi_wstrb : out std_logic_vector(G_AXIL_DATA_WIDTH/8-1 downto 0);
axi_wvalid : out std_logic;
--!write response
axi_bready : out std_logic;
--!read address
axi_araddr : out std_logic_vector(G_AXI_ADDR_WIDTH-1 downto 0);
axi_arprot : out std_logic_vector(2 downto 0);
axi_arvalid : out std_logic;
--!read data
axi_rready : out std_logic;
--write address
axi_awready : in std_logic;
--write data
axi_wready : in std_logic;
--write response
axi_bresp : in std_logic_vector(1 downto 0);
axi_bvalid : in std_logic;
--read address
axi_arready : in std_logic;
--read data
axi_rdata : in std_logic_vector(G_AXIL_DATA_WIDTH-1 downto 0);
axi_rresp : in std_logic_vector(1 downto 0);
axi_rvalid : in std_logic
);
end entity axi_protocol;
architecture rtl of axi_protocol is
constant C_SINGLE_READ : std_logic_vector(7 downto 0) := x"05";
constant C_SINGLE_WRITE : std_logic_vector(7 downto 0) := x"09";
constant C_NUMB_ADDR_BYTES : integer := 4;
constant C_NUMB_LENGTH_BYTES : integer := 1;
constant C_NUMB_DATA_BYTES : integer := 4;
constant C_NUMB_AXIL_DATA_BYTES : integer := 4;
constant C_NUMB_CRC_BYTES : integer := 4;
constant C_MAX_NUMB_BYTES : integer := 4; -- max number of the above constant for number of bytes
constant C_ZERO_PAD : std_logic_vector(7 downto 0) := (others => '0');
type t_fsm is (idle, address, length, dummy, write_payload, read_payload, crc, write_axil, write_axi, read_axi, read_axil);
type t_op_fsm is (idle, output, check);
type t_array is array (0 to 7) of std_logic_vector(31 downto 0);
type axil_read_fsm is (IDLE, START, CHECK_ADDR_RESP, READ_DATA, DONE);
type axil_write_fsm is (IDLE, START, CHECK_ADDR_RESP, WRITE_DATA, RESP_READY, CHECK_RESP, DONE);
signal write_state : axil_write_fsm;
signal read_state : axil_read_fsm;
signal s_current_state : t_fsm;
signal s_command : std_logic_vector(7 downto 0);
signal s_address : std_logic_vector((C_NUMB_ADDR_BYTES * 8)-1 downto 0);
signal s_length : std_logic_vector(7 downto 0);
signal s_length_axi : std_logic_vector(7 downto 0);
signal s_buf_cnt : unsigned(7 downto 0);
signal s_byte_pos : integer range 0 to C_MAX_NUMB_BYTES;
signal s_num_bytes : integer range 0 to C_MAX_NUMB_BYTES;
signal s_s_tready : std_logic;
signal s_write_buffer : t_array :=(others=>(others=>'0'));
signal s_read_buffer : t_array :=(others=>(others=>'0'));
signal s_write_buffer_temp : std_logic_vector(31 downto 0);
signal s_read_buffer_temp : std_logic_vector(31 downto 0);
--axil lite data interface
signal s_axil_data : std_logic_vector(G_AXIL_DATA_WIDTH-1 downto 0);
signal s_axil_valid : std_logic;
signal s_axil_idata : std_logic_vector(G_AXIL_DATA_WIDTH-1 downto 0);
--axi mstream
signal s_opptr : unsigned(7 downto 0);
signal s_start : std_logic;
signal s_op_state : t_op_fsm;
signal s_op_byte : integer range 0 to C_MAX_NUMB_BYTES;
signal start_read : std_logic;
signal start_write : std_logic;
signal s_m_axis_tvalid : std_logic;
begin
s_axis_tready <= s_s_tready;
FSM : process(clk, reset )
begin
if (reset = '0') then
start_read <= '0';
start_write <= '0';
s_s_tready <= '0';
elsif rising_edge(clk) then
s_s_tready <= '1';
s_start <= '0';
start_read <= '0';
start_write <= '0';
case s_current_state is
when idle => -- to do needs to check the command is valid
s_buf_cnt <= (others =>'0');
if (s_axis_tvalid = '1' and s_s_tready = '1') and
(s_axis_tdata = C_SINGLE_READ or s_axis_tdata = C_SINGLE_WRITE) then
s_s_tready <= '0';
s_command <= s_axis_tdata;
s_current_state <= address;
s_byte_pos <= C_NUMB_ADDR_BYTES;
end if;
when address =>
if s_byte_pos = 0 then
s_s_tready <= '0';
s_byte_pos <= C_NUMB_LENGTH_BYTES;
s_current_state <= length;
elsif s_axis_tvalid = '1' and s_s_tready = '1' then
s_address <= s_address(s_address'length-8-1 downto 0) & s_axis_tdata;
s_byte_pos <= s_byte_pos - 1;
if s_byte_pos = 1 then
s_s_tready <= '0';
end if;
end if;
when length =>
if s_byte_pos = 0 then
s_s_tready <= '0';
if s_command = C_SINGLE_READ and unsigned(s_length) = 1 then
s_current_state <= read_axil;
start_read <= '1';
s_num_bytes <= C_NUMB_AXIL_DATA_BYTES;
elsif s_command = C_SINGLE_WRITE then
s_buf_cnt <= (others =>'0');
s_byte_pos <= C_NUMB_AXIL_DATA_BYTES;
s_num_bytes <= C_NUMB_AXIL_DATA_BYTES;
s_current_state <= write_payload;
end if;
elsif s_axis_tvalid = '1' and s_s_tready = '1' then
s_length <= s_axis_tdata;
s_length_axi <= std_logic_vector(unsigned(s_axis_tdata)-1);
s_byte_pos <= s_byte_pos - 1;
s_s_tready <= '0';
end if;
when read_axil =>
if s_axil_valid = '1' then
s_start <= '1';
s_read_buffer(0)(G_AXIL_DATA_WIDTH-1 downto 0) <= s_axil_data;
end if;
if (read_state = DONE) then
s_current_state <= read_payload;
end if;
when write_payload =>
if s_buf_cnt = unsigned(s_length) then
s_s_tready <= '0';
s_current_state <= write_axil;
start_write <= '1';
else
if s_byte_pos = 0 then
s_s_tready <= '0';
s_byte_pos <= s_num_bytes;
s_write_buffer(to_integer(s_buf_cnt)) <= s_write_buffer_temp;
s_buf_cnt <= s_buf_cnt + 1;
elsif (s_axis_tvalid = '1' and s_s_tready = '1') then
s_write_buffer_temp <= s_write_buffer_temp(s_write_buffer_temp'length-8-1 downto 0) & s_axis_tdata;
s_byte_pos <= s_byte_pos - 1;
if s_byte_pos = 1 then
s_s_tready <= '0';
end if;
end if;
end if;
when write_axil =>
s_s_tready <= '0';
start_write <= '1';
s_axil_idata <= s_write_buffer(0);
if (write_state = DONE) then
s_current_state <= idle;
end if;
when read_payload =>
s_current_state <= idle;
when others => null;
end case;
end if;
end process;
m_axis_tvalid <= s_m_axis_tvalid;
process(clk, reset)
begin
if (reset = '0') then
s_m_axis_tvalid <= '0';
m_axis_tdata <= (others =>'0');
s_opptr <= (others => '0');
s_op_byte <= C_NUMB_AXIL_DATA_BYTES;
elsif rising_edge(clk) then
case s_op_state is
when idle =>
s_m_axis_tvalid <= '0';
if s_start = '1' then
s_opptr <= (others => '0');
s_read_buffer_temp <= s_read_buffer(0);
s_op_byte <= s_num_bytes;
s_op_state <= output;
end if;
when output =>
if s_opptr = unsigned(s_length) then
s_op_state <= idle;
s_m_axis_tvalid <= '0';
else
s_m_axis_tvalid <= '1';
m_axis_tdata <= s_read_buffer_temp(7 downto 0);
if s_op_byte = 0 then
s_op_byte <= s_num_bytes;
s_opptr <= s_opptr + 1;
s_m_axis_tvalid <= '0';
elsif m_axis_tready = '1' then
s_m_axis_tvalid <= '1';
s_read_buffer_temp <= C_ZERO_PAD & s_read_buffer_temp(s_read_buffer_temp'length-1 downto 8);
s_op_byte <= s_op_byte - 1;
s_op_state <= check;
end if;
end if;
when check =>
s_m_axis_tvalid <= '0';
s_op_state <= output;
end case;
end if;
end process;
process(clk, reset)
begin
if (reset = '0') then
write_state <= IDLE;
axi_awaddr <= (others =>'0');
axi_awprot <= (others =>'0');
axi_awvalid <= '0';
axi_wdata <= (others =>'0');
axi_wstrb <= (others =>'0');
axi_wvalid <= '0';
axi_bready <= '0';
elsif rising_edge(clk) then
axi_wstrb <= (others =>'0');
case write_state is
--Send write address
when IDLE =>
if start_write = '1' then
write_state <= START;
end if;
when START =>
axi_awaddr <= s_address;
axi_awprot <= "010";
axi_awvalid <= '1';
axi_wdata <= s_axil_idata;
axi_wvalid <= '1';
axi_wstrb <= (others =>'1');
write_state <= WRITE_DATA;--CHECK_ADDR_RESP;
--Wait for slave to acknowledge receipt
when CHECK_ADDR_RESP =>
if (axi_awready = '1' ) then
axi_awaddr <= (others => '0');
axi_awprot <= (others => '0');
axi_awvalid <= '0';
write_state <= WRITE_DATA;
else
write_state <= CHECK_ADDR_RESP;
end if;
--Send write data
when WRITE_DATA =>
if (axi_awready = '1' ) then
axi_awaddr <= (others => '0');
axi_awprot <= (others => '0');
axi_awvalid <= '0';
axi_wstrb <= (others =>'0');
end if;
axi_wdata <= s_axil_idata;
axi_wvalid <= '1';
axi_wstrb <= (others =>'1');
if (axi_wready = '1') then
write_state <= RESP_READY;
else
write_state <= WRITE_DATA;
end if;
--Set response ready
when RESP_READY =>
axi_wstrb <= (others =>'0');
axi_wvalid <= '0';
axi_bready <= '1';
write_state <= CHECK_RESP;
--Check the response
when CHECK_RESP =>
if (axi_bvalid = '1') then
axi_bready <= '0';
write_state <= DONE;
end if;
--Indicate the transaction has completed
when DONE =>
write_state <= IDLE;
when others =>
write_state <= START;
end case;
end if;
end process;
process(clk, reset)
begin
if (reset = '0') then
read_state <= IDLE;
axi_araddr <= (others =>'0');
axi_arprot <= (others =>'0');
axi_arvalid <= '0';
axi_rready <= '0';
elsif rising_edge(clk) then
case read_state is
when IDLE =>
if start_read = '1' then
read_state <= START;
end if;
--Send read address
when START =>
axi_araddr <= s_address;
axi_arprot <= "010";
axi_arvalid <= '1';
s_axil_valid <= '0';
read_state <= CHECK_ADDR_RESP;
--Wait for the slave to acknowledge receipt of the address
when CHECK_ADDR_RESP =>
if (axi_arready = '1' ) then
axi_araddr <= (others => '0');
axi_arprot <= (others => '0');
axi_arvalid <= '0';
read_state <= READ_DATA;
else
read_state <= CHECK_ADDR_RESP;
end if;
s_axil_valid <= '0';
--Read data from the slave
when READ_DATA =>
s_axil_data <= axi_rdata;
if (axi_rvalid = '1') then
s_axil_valid <= '1';
read_state <= DONE;
else
s_axil_valid <= '0';
read_state <= READ_DATA;
end if;
axi_rready <= '1';
--Indicate the transaction has completed
when DONE =>
axi_rready <= '0';
s_axil_data <= (others => '0');
s_axil_valid <= '0';
read_state <= IDLE;
when others =>
read_state <= START;
end case;
end if;
end process;
end architecture;LED RTL
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use ieee.math_real.all;
library Tile_carrier_test_lib;
use Tile_carrier_test_lib.adiuvo_uart.all;
entity led is
generic (
CLK_HZ : positive := 100_000_000; -- input clock frequency
BLINK_HZ : positive := 1 -- desired blink frequency (full period)
);
port (
clk : in std_logic; -- 1 MHz clock
led0 : out std_logic;
led1 : out std_logic
);
end entity led ;
--
architecture rtl of led is
-- Toggle every half-period to make a 50% duty cycle
constant TOGGLE_TICKS : natural := CLK_HZ / (2 * BLINK_HZ); -- = 500_000 for 1MHz/1Hz
signal count : natural range 0 to TOGGLE_TICKS-1 := 0;
signal state : std_logic := '0';
begin
process (clk)
begin
if rising_edge(clk) then
if count = TOGGLE_TICKS - 1 then
count <= 0;
state <= not state; -- flip every 0.5 s → 1 Hz blink
else
count <= count + 1;
end if;
end if;
end process;
led0 <= state;
led1 <= not state; -- opposite phasePWM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_func is port(
resetn : in std_logic;
clk : in std_logic;
pwm_reg : in std_logic_vector(20 downto 0);
pwm_op : out std_logic
);
end entity;
Architecture rtl of pwm_func is
constant max_count : unsigned(20 downto 0) := to_unsigned(1_666_666,21);
signal count : unsigned(20 downto 0);
signal int_target : unsigned(20 downto 0);
begin
process(resetn, clk)
begin
if resetn = '0' then
count <= (others =>'0');
pwm_op <= '0';
int_target <= to_unsigned(150_000,21);
elsif rising_edge(clk) then
if count < int_target then
pwm_op <= '1';
else
pwm_op <= '0';
end if;
if count = max_count then
count <= (others=>'0');
int_target <= unsigned(pwm_reg);
else
count <= count + 1;
end if;
end if;
end process;
end architecture;Top Level
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity top_level is
generic(
G_AXIL_DATA_WIDTH : integer := 32;
G_NUMBER_OF_REGISTERS : integer := 6;
G_S_AXI_DATA_WIDTH : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
rx : in std_logic;
LED0 : out std_logic;
LED1 : out std_logic;
pwm_op : out std_logic;
pwm_op1 : out std_logic;
pwm_op2 : out std_logic;
pwm_op3 : out std_logic;
pwm_op4 : out std_logic;
pwm_op5 : out std_logic;
tx : out std_logic
);
-- Declarations
end entity top_level ;
----------------------------------------------------------------------------------
-- Company: Adiuvo Engineering
-- Engineer: Adam
--
-- Create Date: 13:16:14
-- Design Name: Tile_carrier_test_lib.top_level.struct
-- Target Devices:
-- Tool Versions:
--
-- Dependencies: None
-- Limitations: None
--
-- Revision: Revision 1.0 - File Created
-- Additional Comments:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use ieee.math_real.all;
library Tile_carrier_test_lib;
use Tile_carrier_test_lib.adiuvo_uart.all;
library cl_axi_common;
library ip_axi_pwm;
architecture struct of top_level is
-- Architecture declarations
-- Internal signal declarations
signal axi_araddr : std_logic_vector(31 downto 0);
signal axi_arprot : std_logic_vector(2 downto 0);
signal axi_arready : std_logic;
signal axi_arvalid : std_logic;
signal axi_awaddr : std_logic_vector(31 downto 0);
signal axi_awprot : std_logic_vector(2 downto 0);
signal axi_awready : std_logic;
signal axi_awvalid : std_logic;
signal axi_bready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_rdata : std_logic_vector(31 downto 0);
signal axi_rready : std_logic;
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
signal axi_wdata : std_logic_vector(31 downto 0);
signal axi_wready : std_logic;
signal axi_wstrb : std_logic_vector(G_AXIL_DATA_WIDTH/8-1 downto 0);
signal axi_wvalid : std_logic;
signal i_register_set_qual : std_ulogic_vector(G_NUMBER_OF_REGISTERS - 1 downto 0);
signal i_register_set_value : std_ulogic_vector(G_NUMBER_OF_REGISTERS * G_S_AXI_DATA_WIDTH - 1 downto 0);
signal m_axis_tdata : std_logic_vector(7 downto 0);
signal m_axis_tready : std_logic;
signal m_axis_tvalid : std_logic;
signal o_reg_updated : std_ulogic;
signal o_registers_output : std_ulogic_vector(G_NUMBER_OF_REGISTERS * G_S_AXI_DATA_WIDTH - 1 downto 0);
signal pwm_reg : std_logic_vector(20 downto 0);
signal pwm_reg1 : std_logic_vector(20 downto 0);
signal pwm_reg2 : std_logic_vector(20 downto 0);
signal pwm_reg3 : std_logic_vector(20 downto 0);
signal pwm_reg4 : std_logic_vector(20 downto 0);
signal pwm_reg5 : std_logic_vector(20 downto 0);
signal s_axis_tdata : std_logic_vector(7 downto 0);
signal s_axis_tready : std_logic;
signal s_axis_tvalid : std_logic;
attribute mark_debug : string;
attribute mark_debug of m_axis_tdata: signal is "true";
attribute mark_debug of m_axis_tready: signal is "true";
attribute mark_debug of m_axis_tvalid: signal is "true";
attribute mark_debug of reset: signal is "true";
attribute mark_debug of rx: signal is "true";
-- Component Declarations
component axi_registers
generic (
G_S_AXI_DATA_WIDTH : integer := 32; -- Width of S_AXI data bus
G_S_AXI_ADDR_WIDTH : integer := 6; -- Width of S_AXI address bus
G_NUMBER_OF_REGISTERS : integer := 5; -- Width of S_AXI address bus
G_REGISTER_RESET_VALUES : std_ulogic_vector(G_NUMBER_OF_REGISTERS * G_S_AXI_DATA_WIDTH - 1 downto 0) := (others => '0')
);
port (
i_register_set_qual : in std_ulogic_vector (G_NUMBER_OF_REGISTERS - 1 downto 0);
i_register_set_value : in std_ulogic_vector (G_NUMBER_OF_REGISTERS * G_S_AXI_DATA_WIDTH - 1 downto 0);
i_s_axi_aclk : in std_ulogic;
i_s_axi_araddr : in std_ulogic_vector (G_S_AXI_ADDR_WIDTH-1 downto 0);
i_s_axi_aresetn : in std_ulogic;
i_s_axi_arprot : in std_ulogic_vector (2 downto 0);
i_s_axi_arvalid : in std_ulogic;
i_s_axi_awaddr : in std_ulogic_vector (G_S_AXI_ADDR_WIDTH-1 downto 0);
i_s_axi_awprot : in std_ulogic_vector (2 downto 0);
i_s_axi_awvalid : in std_ulogic;
i_s_axi_bready : in std_ulogic;
i_s_axi_rready : in std_ulogic;
i_s_axi_wdata : in std_ulogic_vector (G_S_AXI_DATA_WIDTH-1 downto 0);
i_s_axi_wstrb : in std_ulogic_vector ((G_S_AXI_DATA_WIDTH/8)-1 downto 0);
i_s_axi_wvalid : in std_ulogic;
o_reg_updated : out std_ulogic;
o_registers_output : out std_ulogic_vector (G_NUMBER_OF_REGISTERS * G_S_AXI_DATA_WIDTH - 1 downto 0);
o_s_axi_arready : out std_ulogic;
o_s_axi_awready : out std_ulogic;
o_s_axi_bresp : out std_ulogic_vector (1 downto 0);
o_s_axi_bvalid : out std_ulogic;
o_s_axi_rdata : out std_ulogic_vector (G_S_AXI_DATA_WIDTH-1 downto 0);
o_s_axi_rresp : out std_ulogic_vector (1 downto 0);
o_s_axi_rvalid : out std_ulogic;
o_s_axi_wready : out std_ulogic
);
end component axi_registers;
component pwm_func
port (
clk : in std_logic;
pwm_reg : in std_logic_vector (20 downto 0);
resetn : in std_logic;
pwm_op : out std_logic
);
end component pwm_func;
component axi_protocol
generic (
G_AXIL_DATA_WIDTH : integer := 32; --Width of AXI Lite data bus
G_AXI_ADDR_WIDTH : integer := 32; --Width of AXI Lite Address Bu
G_AXI_ID_WIDTH : integer := 8; --Width of AXI ID Bus
G_AXI_AWUSER_WIDTH : integer := 1 --Width of AXI AW User bus
);
port (
axi_arready : in std_logic;
axi_awready : in std_logic;
axi_bresp : in std_logic_vector (1 downto 0);
axi_bvalid : in std_logic;
axi_rdata : in std_logic_vector (G_AXIL_DATA_WIDTH-1 downto 0);
axi_rresp : in std_logic_vector (1 downto 0);
axi_rvalid : in std_logic;
axi_wready : in std_logic;
clk : in std_ulogic;
m_axis_tready : in std_logic;
reset : in std_ulogic;
s_axis_tdata : in std_logic_vector (7 downto 0);
s_axis_tvalid : in std_logic;
axi_araddr : out std_logic_vector (G_AXI_ADDR_WIDTH-1 downto 0);
axi_arprot : out std_logic_vector (2 downto 0);
axi_arvalid : out std_logic;
axi_awaddr : out std_logic_vector (G_AXI_ADDR_WIDTH-1 downto 0);
axi_awprot : out std_logic_vector (2 downto 0);
axi_awvalid : out std_logic;
axi_bready : out std_logic;
axi_rready : out std_logic;
axi_wdata : out std_logic_vector (G_AXIL_DATA_WIDTH-1 downto 0);
axi_wstrb : out std_logic_vector (G_AXIL_DATA_WIDTH/8-1 downto 0);
axi_wvalid : out std_logic;
m_axis_tdata : out std_logic_vector (7 downto 0);
m_axis_tvalid : out std_logic;
s_axis_tready : out std_logic
);
end component axi_protocol;
component led
generic (
CLK_HZ : positive := 100_000_000; -- input clock frequency
BLINK_HZ : positive := 1 -- desired blink frequency (full period)
);
port (
clk : in std_logic ;
LED0 : out std_logic ;
LED1 : out std_logic
);
end component led;
component uart
generic (
reset_level : std_logic := '0'; -- reset level which causes a reset
clk_freq : natural := 100_000_000; -- oscillator frequency
baud_rate : natural := 115200 -- baud rate
);
port (
clk : in std_logic;
m_axis_tready : in std_logic;
reset : in std_logic;
rx : in std_logic;
s_axis_tdata : in std_logic_vector (7 downto 0);
s_axis_tvalid : in std_logic;
m_axis_tdata : out std_logic_vector (7 downto 0);
m_axis_tvalid : out std_logic;
s_axis_tready : out std_logic;
tx : out std_logic
);
end component uart;
-- Optional embedded configurations
-- pragma synthesis_off
for all : axi_protocol use entity Tile_carrier_test_lib.axi_protocol;
for all : axi_registers use entity cl_axi_common.axi_registers;
for all : led use entity Tile_carrier_test_lib.led;
for all : pwm_func use entity ip_axi_pwm.pwm_func;
for all : uart use entity Tile_carrier_test_lib.uart;
-- pragma synthesis_on
begin
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
pwm_reg <= o_registers_output(20 downto 0) when o_reg_updated = '1';
pwm_reg1 <= o_registers_output(52 downto 32) when o_reg_updated = '1';
pwm_reg2 <= o_registers_output(84 downto 64) when o_reg_updated = '1';
pwm_reg3 <= o_registers_output(116 downto 96) when o_reg_updated = '1';
pwm_reg4 <= o_registers_output(148 downto 128) when o_reg_updated = '1';
pwm_reg5 <= o_registers_output(180 downto 160) when o_reg_updated = '1';
i_register_set_qual <= (others =>'0');
i_register_set_value <= (others => '0');
-- Instance port mappings.
U_3 : axi_registers
generic map (
G_S_AXI_DATA_WIDTH => 32, -- Width of S_AXI data bus
G_S_AXI_ADDR_WIDTH => 32, -- Width of S_AXI address bus
G_NUMBER_OF_REGISTERS => 6, -- Width of S_AXI address bus
G_REGISTER_RESET_VALUES => (others => '0')
)
port map (
i_s_axi_aclk => clk,
i_s_axi_aresetn => reset,
i_s_axi_awaddr => axi_awaddr,
i_s_axi_awprot => axi_awprot,
i_s_axi_awvalid => axi_awvalid,
o_s_axi_awready => axi_awready,
i_s_axi_wdata => axi_wdata,
i_s_axi_wstrb => axi_wstrb,
i_s_axi_wvalid => axi_wvalid,
o_s_axi_wready => axi_wready,
o_s_axi_bresp => axi_bresp,
o_s_axi_bvalid => axi_bvalid,
i_s_axi_bready => axi_bready,
i_s_axi_araddr => axi_araddr,
i_s_axi_arprot => axi_arprot,
i_s_axi_arvalid => axi_arvalid,
o_s_axi_arready => axi_arready,
o_s_axi_rdata => axi_rdata,
o_s_axi_rresp => axi_rresp,
o_s_axi_rvalid => axi_rvalid,
i_s_axi_rready => axi_rready,
o_reg_updated => o_reg_updated,
i_register_set_qual => i_register_set_qual,
i_register_set_value => i_register_set_value,
o_registers_output => o_registers_output
);
U_2 : pwm_func
port map (
resetn => reset,
clk => clk,
pwm_reg => pwm_reg,
pwm_op => pwm_op
);
U_4 : pwm_func
port map (
resetn => reset,
clk => clk,
pwm_reg => pwm_reg1,
pwm_op => pwm_op1
);
U_5 : pwm_func
port map (
resetn => reset,
clk => clk,
pwm_reg => pwm_reg2,
pwm_op => pwm_op2
);
U_6 : pwm_func
port map (
resetn => reset,
clk => clk,
pwm_reg => pwm_reg3,
pwm_op => pwm_op3
);
U_7 : pwm_func
port map (
resetn => reset,
clk => clk,
pwm_reg => pwm_reg4,
pwm_op => pwm_op4
);
U_8 : pwm_func
port map (
resetn => reset,
clk => clk,
pwm_reg => pwm_reg5,
pwm_op => pwm_op5
);
U_0 : axi_protocol
generic map (
G_AXIL_DATA_WIDTH => 32, --Width of AXI Lite data bus
G_AXI_ADDR_WIDTH => 32, --Width of AXI Lite Address Bu
G_AXI_ID_WIDTH => 8, --Width of AXI ID Bus
G_AXI_AWUSER_WIDTH => 1 --Width of AXI AW User bus
)
port map (
clk => clk,
reset => reset,
m_axis_tready => s_axis_tready,
m_axis_tdata => s_axis_tdata,
m_axis_tvalid => s_axis_tvalid,
s_axis_tready => m_axis_tready,
s_axis_tdata => m_axis_tdata,
s_axis_tvalid => m_axis_tvalid,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_wvalid => axi_wvalid,
axi_bready => axi_bready,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_rready => axi_rready,
axi_awready => axi_awready,
axi_wready => axi_wready,
axi_bresp => axi_bresp,
axi_bvalid => axi_bvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rresp => axi_rresp,
axi_rvalid => axi_rvalid
);
U_9 : led
generic map (
CLK_HZ => 100_000_000, -- input clock frequency
BLINK_HZ => 1 -- desired blink frequency (full period)
)
port map (
clk => clk,
LED0 => LED0,
LED1 => LED1
);
U_1 : uart
generic map (
reset_level => '0', -- reset level which causes a reset
clk_freq => 100_000_000, -- oscillator frequency
baud_rate => 115200 -- baud rate
)
port map (
clk => clk,
reset => reset,
rx => rx,
tx => tx,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tvalid
);
end architecture struct;Test Bench Top Level
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity tb_top is
-- Declarations
end entity tb_top ;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY cl_ver_common;
library Tile_carrier_test_lib;
architecture struct of tb_top is
-- Architecture declarations
-- Internal signal declarations
signal LED0 : std_logic;
signal LED1 : std_logic;
signal clk : std_logic;
signal pwm_op : std_logic;
signal pwm_op1 : std_logic;
signal pwm_op2 : std_logic;
signal pwm_op3 : std_logic;
signal pwm_op4 : std_logic;
signal pwm_op5 : std_logic;
signal reset : std_logic;
signal rx : std_logic;
signal tx : std_logic;
-- Component Declarations
component tb_stim
port (
tx : in std_logic ;
clk : out std_logic ;
reset : out std_logic ;
rx : out std_logic
);
end component tb_stim;
component top_level
generic (
G_AXIL_DATA_WIDTH : integer := 32;
G_NUMBER_OF_REGISTERS : integer := 6;
G_S_AXI_DATA_WIDTH : integer := 32
);
port (
clk : in std_logic ;
reset : in std_logic ;
rx : in std_logic ;
LED0 : out std_logic ;
LED1 : out std_logic ;
pwm_op : out std_logic ;
pwm_op1 : out std_logic ;
pwm_op2 : out std_logic ;
pwm_op3 : out std_logic ;
pwm_op4 : out std_logic ;
pwm_op5 : out std_logic ;
tx : out std_logic
);
end component top_level;
-- Optional embedded configurations
-- pragma synthesis_off
for all : tb_stim use entity Tile_carrier_test_lib.tb_stim;
for all : top_level use entity Tile_carrier_test_lib.top_level;
-- pragma synthesis_on
begin
-- Instance port mappings.
U_1 : tb_stim
port map (
tx => tx,
clk => clk,
reset => reset,
rx => rx
);
U_0 : top_level
generic map (
G_AXIL_DATA_WIDTH => 32,
G_NUMBER_OF_REGISTERS => 6,
G_S_AXI_DATA_WIDTH => 32
)
port map (
clk => clk,
reset => reset,
rx => rx,
LED0 => LED0,
LED1 => LED1,
pwm_op => pwm_op,
pwm_op1 => pwm_op1,
pwm_op2 => pwm_op2,
pwm_op3 => pwm_op3,
pwm_op4 => pwm_op4,
pwm_op5 => pwm_op5,
tx => tx
);
end architecture struct;TB Stim
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library cl_ver_common;
package uart_tb_uart_pkg is new cl_ver_common.uart_bfm_pkg generic map (G_ENDIANESS => "LSB", G_BAUD_RATE => 115200.0, G_PARITY_ODD => 1);
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY cl_ver_common;
entity tb_stim is
port(
tx : in std_logic;
clk : out std_logic;
reset : out std_logic;
rx : out std_logic
);
-- Declarations
end entity tb_stim ;
--
architecture behave of tb_stim is
constant clk_period : time := 10 ns;
constant c_trst : time := 100 us;
signal s_clk : std_logic := '0';
signal s_reset : std_logic := '0';
signal s_uart_miso : work.uart_tb_uart_pkg.r_miso;
signal s_uart_mosi : work.uart_tb_uart_pkg.r_mosi;
begin
clk <= s_clk;
s_clk <= not s_clk after (clk_period/2);
reset <= s_reset;
process begin
wait for c_trst;
s_reset <= '1';
wait;
end process;
rx <= s_uart_mosi.s_tx;
s_uart_miso.s_rx <= tx;
stim : process
begin
wait until s_reset = '1';
work.uart_tb_uart_pkg.transmit(09, s_uart_mosi, "yes"); -- command Write
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes");--length
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(23, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(45, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(67, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(09, s_uart_mosi, "yes"); -- command Write
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(04, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes");--length
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(23, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(45, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(67, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(09, s_uart_mosi, "yes"); -- command Write
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(08, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes");--length
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(23, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(45, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(67, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(09, s_uart_mosi, "yes"); -- command Write
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(12, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes");--length
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(23, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(45, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(67, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(09, s_uart_mosi, "yes"); -- command Write
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(16, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes");--length
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(23, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(45, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(67, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(09, s_uart_mosi, "yes"); -- command Write
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(00, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(20, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes");--length
wait for 100 us;
work.uart_tb_uart_pkg.transmit(01, s_uart_mosi, "yes"); --address
wait for 100 us;
work.uart_tb_uart_pkg.transmit(23, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(45, s_uart_mosi, "yes");
wait for 100 us;
work.uart_tb_uart_pkg.transmit(67, s_uart_mosi, "yes");
wait for 1000 us;
report "simulation complete" severity failure;
end process;
end architecture behave;The constraints for the connection between the Embedded System Tile, RPi CM5 and Pmods is shown below.
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports LED0]
set_property IOSTANDARD LVCMOS33 [get_ports LED1]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_op]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_op1]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_op2]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_op3]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_op4]
set_property IOSTANDARD LVCMOS33 [get_ports pwm_op5]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property IOSTANDARD LVCMOS33 [get_ports tx]
set_property PACKAGE_PIN M9 [get_ports clk]
set_property PACKAGE_PIN N6 [get_ports LED0]
set_property PACKAGE_PIN N7 [get_ports LED1]
set_property PACKAGE_PIN M1 [get_ports pwm_op]
set_property PACKAGE_PIN K3 [get_ports pwm_op1]
set_property PACKAGE_PIN K1 [get_ports pwm_op2]
set_property PACKAGE_PIN J4 [get_ports pwm_op3]
set_property PACKAGE_PIN N1 [get_ports pwm_op4]
set_property PACKAGE_PIN N3 [get_ports pwm_op5]
set_property PACKAGE_PIN F2 [get_ports reset]
set_property PACKAGE_PIN k15 [get_ports rx]
set_property PACKAGE_PIN j15 [get_ports tx]Implementing this design on the Embedded System Tile results in the following resource utilization in the final implementation.
We can then program the.bin file into the Embedded System Tile’s configuration memory and set the mode switch to boot from the QSPI memory.
If you want to follow along with this project, you will need an Edge Impulse account.
To get started with this project, we are going to clone an existing Edge Impulse Experts Face Detection project, which is linked below here
Click the Clone Project button on the Face Detection demo. This will create a copy of the project in your Edge Impulse Studio account.
With the project successfully cloned, the next step is to change the target device. In this case, I selected the Raspberry Pi 5 as the target.
With the target device updated, we can now regenerate the deployable Linux image. This image will be used to run the project on the Tile Carrier Card. However, before doing so, we must first ensure that the Raspberry Pi CM5 is properly prepared.
The first step is to ensure that all packages on the system are up to date. We can do this using the following commands:
curl -sL https://deb.nodesource.com/setup_20.x | sudo -E bash -
sudo apt install -y gcc g++ make build-essential nodejs sox gstreamer1.0-tools gstreamer1.0-plugins-good gstreamer1.0-plugins-base gstreamer1.0-plugins-base-apps
npm install -g edge-impulse-linuxThis will take a few minutes to install the packages,
If prompted, make sure to update NPM using the following command:
sudo npm install -g npm@10.8.1We can now start the Edge Impulse Linux app and connect it to our cloned project in Edge Impulse Studio.
edge-impulse-linux --cleanUsing the --clean command allows you to define and connect to a new project instead of reusing an existing configuration. This is helpful if you want to start fresh or link the device to a different Edge Impulse project..
Once this setup is complete, we can connect a USB webcam to the Raspberry Pi CM5. This will allow the Edge Impulse application to capture live video input for face detection and testing.
We can then use Edge Impulse Studio to test the model in real time, utilizing the USB webcam connected to the Tile Carrier Card. This allows us to verify that the face detection model is functioning correctly and that it can recognize faces as expected.
With the project connected to our Tile Carrier Card, it’s time to create an application that can run on the Tile Carrier Card without requiring a connection to Edge Impulse Studio. In the current setup, the model is executed in the cloud via Edge Impulse Studio, with the RPi CM5 connected.
Deployable SolutionTo run the model on the RPi CM5 without a connection to Edge Impulse Studio, we first need to install the Edge Impulse Python SDK.
pip3 install edge_impulse_linuxWe also need to install OpenCV and pySerial, as they are essential for handling image processing and serial communication, respectively. You can install them using the following commands:
pip3 install opencv-python pyserialOpenCV will be used to capture and process video frames from the USB webcam.
- pySerial will handle communication between the RPi CM5 and the Embedded System Tile over the UART interface.
- With these packages installed, the Raspberry Pi CM5 will have everything needed to run the face detection model locally and send control commands to the FPGA.
We may also need to install portaudio19-dev and pyAudio
sudo apt-get install portaudio19-dev
pip install pyAudioWith the necessary frameworks installed, we can develop the main application. This application captures images from the webcam using OpenCV and classifies them with the Edge Impulse model running locally on the RPi CM5.
It also displays the webcam feed in a pop-up window showing the model’s processing frame rate.
If a face is detected, the script sends a series of commands over UART to the Embedded System Tile to move specific joints on the connected robot arm and make it wave hello.
import argparse
import time
import struct
import serial
import cv2
import numpy as np
from typing import Dict, Any, Optional
from edge_impulse_linux.image import ImageImpulseRunner
# -------------------- Config --------------------
FACE_LABEL = "face"
THRESHOLD = 0.6
COOLDOWN_S = 1.0
# Joint map (addr per your spec)
JOINT_ADDR: Dict[str, int] = {
"shoulder": 0x0,
"elbow": 0x4,
"wrist": 0x8,
"gripper": 0xc,
"base": 0x10,
}
# UART + PWM protocol (per your spec)
PWM_CLOCK_HZ = 100_000_000
WRITE_CMD = 0x09 # [0x09][Addr3..0][0x01][data3..0]
# ---------------- Robot helpers ----------------
def pulse_to_count(pulse_width_s: float) -> int:
return int(pulse_width_s * PWM_CLOCK_HZ)
def degrees_to_ms(angle_deg: float) -> float:
a = max(-90.0, min(90.0, float(angle_deg)))
return 1.5 + (a / 90.0) * 0.5 # -90�=1.0ms, 0�=1.5ms, +90�=2.0ms
def build_packet(address: int, data: int) -> bytes:
return bytes([WRITE_CMD]) + struct.pack(">I", address) + bytes([0x01]) + struct.pack(">I", data)
def send_pwm_ms(ser: serial.Serial, joint: str, ms: float):
addr = JOINT_ADDR[joint]
ser.write(build_packet(addr, pulse_to_count(ms / 1000.0)))
time.sleep(0.005)
def send_angle(ser: serial.Serial, joint: str, deg: float):
ms = degrees_to_ms(deg)
send_pwm_ms(ser, joint, ms)
print(f"{joint:<8} -> {deg:>6.1f} deg ({ms:.3f} ms)")
def move_all_nominal(ser: serial.Serial):
for j in JOINT_ADDR:
send_angle(ser, j, 0.0)
time.sleep(0.02)
def _ramp(ser: serial.Serial, joint: str, start: float, end: float, step: float = 5.0, delay: float = 0.02):
cur = start
step = abs(step) if end >= start else -abs(step)
while (step > 0 and cur < end) or (step < 0 and cur > end):
cur += step
if (step > 0 and cur > end) or (step < 0 and cur < end):
cur = end
send_angle(ser, joint, cur)
time.sleep(delay)
def wave_motion(ser: serial.Serial):
"""Raise elbow to +45�, wave wrist side-to-side while opening/closing gripper, then return."""
print("Starting wave gesture...")
# Step 1: lift elbow up 45�, keep base/shoulder neutral
send_angle(ser, "base", 0)
send_angle(ser, "shoulder", 0)
_ramp(ser, "elbow", 0, -45)
send_angle(ser, "wrist", 0)
send_angle(ser, "gripper", 0)
time.sleep(0.3)
# Step 2: wave wrist side-to-side while alternating gripper
wrist_angles = [+25, -25] * 3 # 3 cycles
for angle in wrist_angles:
send_angle(ser, "wrist", angle)
send_angle(ser, "gripper", +35 if angle > 0 else -35)
time.sleep(0.35)
# Step 3: return to neutral
send_angle(ser, "wrist", 0)
send_angle(ser, "gripper", 0)
time.sleep(0.3)
# Step 4: lower elbow
_ramp(ser, "elbow", +45, 0)
print("Wave complete ? returning to nominal.")
# --------------- EI result helpers ---------------
def as_float(v: Any, default: float = 0.0) -> float:
if isinstance(v, (int, float)): return float(v)
if isinstance(v, str):
try: return float(v)
except: return default
if isinstance(v, dict):
for k in ("value", "score", "confidence"):
if k in v: return as_float(v[k], default)
if v: return as_float(next(iter(v.values())), default)
return default
def result_score(bb: dict) -> float:
if not isinstance(bb, dict): return 0.0
if "value" in bb: return as_float(bb["value"], 0.0)
if "score" in bb: return as_float(bb["score"], 0.0)
if "confidence" in bb: return as_float(bb["confidence"], 0.0)
return 0.0
def face_detected(res: dict, label: str, thr: float) -> bool:
r = res.get("result", {})
# Object detection path
if isinstance(r.get("bounding_boxes"), list):
for bb in r["bounding_boxes"]:
if str(bb.get("label","")).lower() == label.lower() and result_score(bb) >= thr:
return True
# Classification path
cls = r.get("classification")
if isinstance(cls, dict):
return as_float(cls.get(label, 0.0)) >= thr
return False
# --------------- Drawing (cropped image) ---------------
def draw_boxes_on_cropped(cropped_bgr: np.ndarray, res: dict) -> np.ndarray:
out = cropped_bgr.copy()
r = res.get("result", {})
if isinstance(r.get("bounding_boxes"), list):
for bb in r["bounding_boxes"]:
x = int(as_float(bb.get("x", 0)))
y = int(as_float(bb.get("y", 0)))
w = int(as_float(bb.get("width", 0)))
h = int(as_float(bb.get("height", 0)))
lbl = str(bb.get("label", "obj"))
sc = result_score(bb)
cv2.rectangle(out, (x, y), (x + w, y + h), (0,255,0), 2)
cv2.putText(out, f"{lbl} {sc:.2f}", (x, y - 6),
cv2.FONT_HERSHEY_SIMPLEX, 0.6, (0,255,0), 2)
else:
cls = r.get("classification")
if isinstance(cls, dict):
items = sorted([(k, as_float(v)) for k,v in cls.items()], key=lambda x: x[1], reverse=True)[:3]
y0 = 24
for name, sc in items:
cv2.putText(out, f"{name}: {sc:.2f}", (10, y0),
cv2.FONT_HERSHEY_SIMPLEX, 0.8, (255,255,255), 2)
y0 += 28
return out
# ---------------------- Main ----------------------
def main():
ap = argparse.ArgumentParser()
ap.add_argument("--model", required=True, help=".eim path")
ap.add_argument("--port", required=True, help="Serial port (/dev/ttyUSB0, COMx)")
ap.add_argument("--cam", type=int, default=0)
ap.add_argument("--label", default=FACE_LABEL)
ap.add_argument("--thr", type=float, default=THRESHOLD)
ap.add_argument("--cooldown", type=float, default=COOLDOWN_S)
ap.add_argument("--swap-colors", action="store_true",
help="Swap color channels for display if colors look swapped")
args = ap.parse_args()
# Serial (115200, odd parity, 2 stop bits)
ser = serial.Serial(
port=args.port,
baudrate=115200,
bytesize=serial.EIGHTBITS,
parity=serial.PARITY_ODD,
stopbits=serial.STOPBITS_TWO,
timeout=1
)
print("Serial connected. Moving to nominal...")
move_all_nominal(ser)
# Camera
cap = cv2.VideoCapture(args.cam)
if not cap.isOpened():
ser.close()
raise SystemExit("Could not open camera")
# Edge Impulse (official pattern)
runner = ImageImpulseRunner(args.model)
info = runner.init()
print("Loaded model:", info.get("project"))
last_wave_ts = 0.0
fps_t = time.time(); fps = 0.0
try:
while True:
ok, frame = cap.read()
if not ok:
break
try:
# EI OFFICIAL: get_features_from_image(frame) then classify(features)
features, cropped = runner.get_features_from_image(frame)
res = runner.classify(features)
except Exception as e:
print("Runner classify error:", e)
time.sleep(0.02)
continue
# Basic FPS
now = time.time()
fps = 1.0 / max(1e-6, (now - fps_t))
fps_t = now
# Trigger wave if face found
status = ""
if face_detected(res, args.label, args.thr):
if now - last_wave_ts >= args.cooldown:
status = f"'{args.label}' >= {args.thr:.2f} ? waving!"
wave_motion(ser)
last_wave_ts = now
else:
status = f"Detected; cooldown {args.cooldown - (now - last_wave_ts):.1f}s"
# Show what the model actually saw (cropped)
if cropped is not None:
cropped_disp = frame
#if args.swap_colors:
# For some setups colors are reversed (BGR/RGB mismatch)
# cropped_disp = cv2.cvtColor(cropped, cv2.COLOR_RGB2BGR)
#else:
# cropped_disp = cv2.cvtColor(cropped, cv2.COLOR_BGR2RGB)
else:
cropped_disp = frame
#if args.swap_colors:
# For some setups colors are reversed (BGR/RGB mismatch)
# cropped_disp = cv2.cvtColor(frame, cv2.COLOR_RGB2BGR)
#else:
# cropped_disp = cv2.cvtColor(frame, cv2.COLOR_BGR2RGB)
vis = draw_boxes_on_cropped(cropped_disp, res)
cv2.putText(vis, f"FPS: {fps:.1f}", (10, vis.shape[0]-10),
cv2.FONT_HERSHEY_SIMPLEX, 1, (50,255,255), 2)
if status:
cv2.putText(vis, status, (10, 28), cv2.FONT_HERSHEY_SIMPLEX, 0.8, (255,50,50), 2)
cv2.imshow("Adiuvo Engineering", vis)
if cv2.waitKey(1) & 0xFF == ord('q'):
break
time.sleep(0.005)
except KeyboardInterrupt:
print("Interrupted by user.")
finally:
print("Returning to nominal...")
try: move_all_nominal(ser)
except Exception: pass
try: runner.stop()
except Exception: pass
cap.release()
ser.close()
cv2.destroyAllWindows()
if __name__ == "__main__":
main()You can see an example of this in the image below.
Running the application demonstrates the system in action, as shown below. The webcam feed is displayed on-screen, and when a face is detected, the robot arm responds by performing a simple wave, confirming successful communication between the RPi CM5, the Embedded System Tile, and the connected actuators.
Wrap UpThis project has demonstrated that the Tile Carrier Card and the Embedded System Tile can be seamlessly combined to create a simple face detection AI application. The system integrates robotics and AI, enabling physical interaction, in this case, a robot arm wave, triggered by the results of the AI model.
It showcases how embedded processing, FPGA control, and AI inference can work together to deliver intelligent, responsive behavior in a compact and flexible prototyping platform.
149 projects • 2532 followers
Adam Taylor is an expert in design and development of embedded systems and FPGA’s for several end applications (Space, Defense, Automotive)
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