05 Create your custom Configurable Example Design in Vivado

Introduction

One way to get started with a new AMD Vivado™ project is to use the Configurable Example Designs.

The Configurable Example Designs (CED) are pre-built project examples provided by AMD that demonstrate the functionality and usage of various Intellectual Property (IP) cores or specific design methodologies within the Vivado Design Suite. To access the CEDs, simple click on Open Example Project in the Vivado welcome page (or click File > Project > OpenExample).

On nice thing about these CED is that they are templatized so you have settings you can use to configure different version of a design

These configurable example designs are also provided in a GitHub repository:

https://github.com/Xilinx/XilinxCEDStore

Thus this is easy to replicate the code if you want to create your own configurable example design.

If you want to work with AI Engine, as I do on my Trenz TE0950 board following up with my previous project, you need to use the Vitis Acceleration flow. In the Vitis Acceleration flow, you start by creating an hardware platform in Vivado. In Versal devices, this platform will contain the CIPS and the NoC IP, clocks, resets and IO related IPs. Then you export this HW platform to Vitis which will add processing kernels and connect them and the AI Engine to the HW platform.

You can then complete you design in Vitis or move back to AMD Vivado. The AMD Vitis acceleration flow is documented AMD UG1701:

https://docs.amd.com/r/en-US/ug1701-vitis-accelerated-embedded/Getting-Started-with-Vitis-Unified-Software-Platform

One good way to create your base HW platform if you are targeting a AMD Evaluation board is to use a Vivado Configurable Example Design named VersalExtensible Platform as this contains all the required element to complete a design with Vitis.

If you are not using an AMD board, for example for me the Trenz TE0950 board, this CED is not available. There is another one which is recommended which is the VersalExtensible Platform(Part Based). This is basically the same design but targeting the part directly.

However, if you create the design targeting the part, one limitation is that you cannot use the board predefined settings (if the vendor is providing a well defined board file or you have created it for your custom board) for the CIPS and NoC IPs as I have used in previous projects (see 02 and 03). So you would need to change the settings manually as this is shown in the following tutorial from AMD:

https://github.com/Xilinx/Vitis-Tutorials/blob/2025.1/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md

As the code for the CED is available on GitHub I wanted to try to create my own configurable example design which could create a Vitis Extensible platform and use board pre-defined settings.

Custom Configurable Example Design

This is how I did to create my own configurable example design:

First I copied locally the VersalExtensible Platform(Part Based) example that I got from GitHub:

https://github.com/Xilinx/XilinxCEDStore/tree/2025.1/ced/Xilinx/IPI/Versal_Extensible_Embedded_Platform_Part

Note that I did not set the same hierarchy as in the GitHub repo to see if this was important for the tool to pickup the example. So I simply copied the Versal_Extensible_Embedded_Platform_Part folder into a folder named example.

Then to see if the tool could find my example I had to find a way of identifying it in Vivado. For this I have found the design.xml file which seemed to contains the name and "vendor" of the example. I modified to put a new name VersalExtensible Platform(CustomBoards) and a new vendor (xflorentw as my GitHub username):

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>

<ExampleDesign>

<Vendor>xflorentw</Vendor>

<Library>design</Library>

<Name>ext_platform_board</Name>

<DisplayName>Versal Extensible Embedded Platform (Custom Board based)</DisplayName>

<Description>An extensible platform is the foundation of the Vitis software acceleration flow. This platform enables Vitis to create AIE kernels and PL kernels. It gives the kernels access to DDR memory, an interrupt controller, and clocking resources. Extensible interfaces are marked with PFM properties and the platform is exported to Vitis using write_hw_platform to create an XSA.</Description>

Then for Vivado to find the design, we have to give the path in the Vivado_inti.tcl file (located under ~/.Xilinx/Vivado):

set_param ced.repoPaths [list "/home/xflorentw/example"]

To verify that this was picked up, I started Vivado 2025.1 and clicked on Open Example Project. I could find the example under xflorentw so the tool was correctly finding it. I could more to modifying the script to create my own example design.

I could then start editing the files to create my own example.

I noticed that there were 2 TCL files which seemed to be important in the process:

• init.tcl contains the parameters for the wizard
• run.tcl contains the TCL commands to create the design (so it is run after clicking finish in the wizard)

So I started by editing the init.tcl file. I first enabled the Trenz TE0950 board (as well as the AMD VCK190 and VEK280):

proc getSupportedBoards {} {
	set V_board_unique [get_board_parts -filter {(BOARD_NAME =~"*vck190*" && VENDOR_NAME=="xilinx.com")||(BOARD_NAME =~"*vek280*" && VENDOR_NAME=="xilinx.com")||(BOARD_NAME =~"te0950*" && VENDOR_NAME=="trenz.biz")} -latest_file_version]
	return $V_board_unique
}

If needed, we could just add more boards to this filter so we could select them while creating the project.

I also reduced the number of options in the project to avoid potential failing cases. For example, I removed the option to select BDC just to simplify the example but that can probably work as well.

Then once gain I tested in Vivado that my changes were correctly working. I could select the Trenz TE0950 board and my options were visible in the wizard

Finally I edited the run.tcl file to add the board automation to while creating the CIPS and NoC and I cleaned the file removing any unnecessary commands for my purpose

apply_bd_automation -rule xilinx.com:bd_rule:cips -config { board_preset {Yes} boot_config {Custom} configure_noc {Add new AXI NoC} debug_config {JTAG} design_flow {Full System} mc_type {None} num_mc {1} pl_clocks {0} pl_resets {0}}  [get_bd_cells CIPS_0]
apply_bd_automation -rule xilinx.com:bd_rule:axi_noc -config { hbm_density {None} hbm_internal_clk {0} hbm_nmu {None} mc_type {DDR} noc_clk {None} num_axi_bram {None} num_axi_tg {None} num_aximm_ext {None} num_mc_ddr {1} num_mc_lpddr {None} pl2noc_apm {0} pl2noc_cips {1}}  [get_bd_cells noc_ddr4]

And I tried to build the project to ensure my commands were right. I could get the project built with no error.

Conclusion

While I still need to build a full system in Vitis and test if the parameters are correct (if I can build in Vitis and get an output on the UART) - this is what I will do in the next project - this example was a good learning exercise about the AMD Vivado Configurable Example Project. I have now a way of sharing easily configurable designs with a nice input from a wizard.

And I hope I could use the example I am sharing here to get started with AMD Vitis Acceleration flow with multiple other boards from other vendors without the need of doing any modification to the design (apart from enabling the boards in init.tcl)

If you want to see the final version of my example design, this is all available on my personal GitHub:

https://github.com/xflorentw/TE0950_Designs/tree/main/04_AMD_Vivado_Custom_Configurable_Example

Disclaimers

• AMD, Versal, and Vitis are trademarks or registered trademarks of Advanced Micro Devices, Inc.
• Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.