03 Minimal Baremetal System (with DDR) on Trenz TE0950 Board

Introduction

In this design we are exploring the creation of a minimal system running a Baremetal application on the A72 of the Trenz TE0950 board. The application is running from DDR. The design is an addition of the one created in the previous project.

AMD Vivado™ Project

In this first section we are creating a minimal AMD Vivado project which will only include the CIPS.

Start by creating a new AMD Vivado project targeting the TE0950 and create a new block design

Add a CIPS IP and Click on Run Block Automation to configue the CIPS with the board settings. Keep the default options in the Block Automation window and click OK

Add AXI NoC IP from the IP catalog and click again on Run Block Automation. Keep the default settings and click OK

Note: You can see from the design automation that the tools is enabling one memory controller to access the DDR

Double-click on the CIPS IP, to open its configuration wizard. Click next and PS-PMC.

In the NoC section, enable the NoC Non-Coherent Interfaces PS to NoC Interface 0/1. Click OK then Finish

Double-click the NoC IP. From the General Tab, set Number of AXI Slave interfaces and AXI Clocks to 8

From the Inputs tab, configure S06 AXI and S07 AXI as PS Non-Coherent

From the Connectivity tab, enable a connectivity between respectivly S06_AXI, S07_AXI and MC Port 2 and MC Port 3 and click OK to close the NoC IP configuration GUI

Connect respectively the CIPS interfaces FPD_AXI_NOC_0 and FPD_AXI_NOC_1 to the NoC Interfaces S06_AXI and S07_AXI. Also connect respectively the clocks from the CIPS fpd_axi_noc_axi0_clk and fpd_axi_noc_axi1_clk to the NoC clock input ports aclk6 and aclk7

Right-click in the white space of the Block Diagram view and select Validate Design. Alternatively, you can press the F6 key. The Vivado tool will prompt you to map the IPs in the design to an address. Click Yes.

Click Hierarchy and Expand Design Sources Folder, right-click on the Block Design and select Create HDL Wrapper. Select Let Vivado manage wrapper and auto-update and click OK.

Right-click on the Block Design on more time and select Generate Output Products. Click Generate.

In the Flow navigator, click on Generate Device Image

AMD Vitis™ Workspace

In this second section we are creating a fixed embedded platform with a baremetal domain and configuring it to run from DDR. Then we are creating an application component with an Hello World application and running on the board using JTAG

First we are creating the platform component

Open AMD Vitis and select a workspace

Click on File > New Component > Platform

Set the name of the platform, for example TE0950_basic_DDR, and click Next

Select the XSA which was generated from the Vivado Project and click Next and Finish

Set the following settings:

• Operating system: standalone
• Processor: psv_cortexa72_0
• Select Compiler: GCC Compiler

In the Vitis Flow navigator, click on Build for the TE0950_basic_DDR platform component

Then we are creating the application component for the baremetal application

Click on File > New Component > Application

Name the component TE0950_basic_DDR_hello and click Next

Select the TE0950_basic_DDR platform created previously and click Next

Select standalone_psv_cortexa72_0 as the target domain and click Next

Add the folder src folder from my git repository and click Next and then Finish

The only difference you will find compared to the previous project is the linker script (lscript.ld). In this application, the full code will be implemented in DDR (memory which was not available in the other platform)

In the flow navigator, make sure TE0950_basic_DDR_hello is selected and click Buil

Finally we will run the application through JTAG. The following steps assume the following switch configuration on the TE0950:

• S2 [1:3] - [OFF, OFF, OFF] - JTAG Boot
• S4 [1:3] - [OFF, ON, OFF] - Only the Versal device in the chain

The board also needs to be connected to a PC using a USB cable plugged in J2

If the TE0950 is connected locally to the PC running Vitis go directly to step 6. If the board is connected to a remote PC, start from step 1.

1. On the remote PC, get the IP address (make sure you can ping the PC running Vitis)

2. Still on the remote PC, run Vivado HW server (you need to have Vivado or Vivado Lab Edition installed)

3. In Vitis click Vitis > Target Connection...

4. Click on the + icon to add a new target

5. Set a target Name and add the IP address of the Host. If the board is connected and Powered ON, you should see the xcve2302 device listed under Advanced. Click OK to confirm the settings

6. In the flow navigator, click on the configuration icon which appears when you hover the right side of the Run line with your mouse

7. Make sure the Target Connection is set to the remote one you have configured in step 1 to 5 if the board is connected remotely. If the board is connected on the machine running Vitis, just set the setting to local

Open a UART terminal (for example Tera Term) can connect to the COM port corresponding to the TE0950 board with the following settings

• Speed: 115200
• Data: 8-bit
• Parity: None
• Stop Bits: 1 bit

In Vitis, click on Run in the Flow navigator

In your serial terminal you will see the output from the Versal PLM then the Hello World messages from the application

This means that our NoC is configured well to access the DDR. Now my next step will be to build a linux system using petalinux to run on the board

The full project can be build from Makefile and is available on my github repository

https://github.com/xflorentw/TE0950_Designs/tree/main/02_TE0950_basic_DDR

Disclaimers

• AMD, Versal, and Vitis are trademarks or registered trademarks of Advanced Micro Devices, Inc.
• Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.