02 Minimal Baremetal System (no DDR) on Trenz TE0950 Board

Introduction

In the previous project, I have tested my Trenz TE0950 to make sure it fully functional and we can get the output from the PS UART.

Now I want to get started creating my own design from scratch in AMD Vivado™ ML Design Suite. In this example I will just make sure I can get the CIPS (Control, Interfaces & Processing System), which is the Processing System, properly configured by simply running a baremetal Hello World application on the A72 running from On-Chip memory (no DDR involved yet, that will be for the next article).

AMD Vivado™ Project

In this first section we are creating a minimal AMD Vivado project which will only include the CIPS.

The best way to start an AMD Vivado project targeting a board is to use the board files. For AMD evaluation boards, the board files are part of the installation so we can directly use them. For third-party boards, if they are provided by the board vendors, we have to add them to the tools. There are 2 options for that:

• Using the board store in Vivado
• Downloading the boarfiles directly from the vendor.

Some vendors are providing the board files for their board on the Xilinx Board Store. The Xilinx Board store is basically a git repository with all the board files:

https://github.com/Xilinx/XilinxBoardStore

The board files which are on this repository can be downloaded directly from AMD Vivado.

To download the board from the board store we need to get into the Vivado store.

1. Open Vivado (2025.1)

2. Click Tools > Vivado Store...

3. Select Boards

Only the board which are available in the AMD Vivado Installation are shown. Clicking on the Refresh option at the bottom will fetch the git repository

When clicking on the refresh option, we can see that Trenz is providing the board files for many of they boards with AMD devices but unfortunately not for Versal devices yet.

This lead us to the second option, which is to download the board files from the vendors. Luckily Trenz is providing the TE0950 board files through their web page.

The board files are included in the reference design files we have downloaded in the previous project, under te0950-rd/board_files/TE0950_23_1lse/1.2.

To these board files inside AMD Vivado we have to inform the tool about the location of these board files. There are again multiple options for that. You can go into the tools settings (Tools > Settings) and add the path under Vivado Store > Board repository.

However this will only be available in this specific version of Vivado. I am more in favor of another solution which is to use the Vivado_init.tcl file.

The Vivado_init.tcl is a file which is executed at the start of AMD Vivado. On Linux, it is located under ~/.Xilinx/Vivado. If it does not exist you can simply create a new one.

The TCL command to set a new repository for the board is the following:

set_param board.repoPaths <custom board repo>

One thing to be aware of that I faced is that if you just set a path like this, it will overwrite other repo paths which are set by the tool such as the path for the Vivado board store (so the board files you downloaded from the board store will not be shown in the project creation wizard).

The way I have solved that is by reading first the value of the board.repoPaths setting and adding my custom path:

set boardrepo [get_param board.repoPaths]
set customRepo "/home/xflorentw/My_boards_repo/"


if {[string first "My_boards_repo" [get_param board.repoPaths]] == -1} {
    set boardrepos "${boardrepo} ${customRepo}"
	set_param board.repoPaths $boardrepos
}

With the board files added to the Vivado board repo paths, we are able to create a project targeting the Trenz TE0950 board in AMD Vivado 2025.1

When the project is created, I am creating a new block design and adding the CIPS IP inside it

The board files that we have for the TE0950 contains the settings for the CIPS for this specific board (for example which UART controllers is used on which ports). As the tools finds those settings, it suggests to run the block automation tool:

We can just keep the default settings for this project:

Click Hierarchy and Expand Design Sources Folder, right-click on the Block Design and select Create HDL Wrapper. Select Let Vivado manage wrapper and auto-update and click OK.

Right-click on the Block Design on more time and select Generate Output Products. Click Generate.

In the Flow navigator, click on Generate Device Image. This will create an XSA file that we will use in AMD Vitis™

AMD Vitis™ Workspace

In this second section we are creating a fixed embedded platform with a baremetal domain. Then we are creating an application component with an Hello World application and running on the board using JTAG

First we are creating the platform component

Open Vitis and select a workspace

Click on File > New Component > Platform

Set the name of the platform, for example TE0950_basic, and click Next

Select the XSA which was generated from the Vivado Project and click Next

Set the following settings:

• Operating system: standalone
• Processor: psv_cortexa72_0
• Select Compiler: GCC Compiler

In the Vitis Flow navigator, click on Build for the TE0950_basic platform component

Then we are creating the application component for the baremetal application

Click on File > New Component > Application

Name the component TE0950_basic_hello and click Next

Select the TE0950_basic platform created previously and click Next

Select standalone_psv_cortexa72_0 as the target domain and click Next

Add the folder src folder from my git repository https://github.com/xflorentw/TE0950_Designs/tree/main/01_TE0950_basic/vitis/src and click Next and then Finish

In the flow navigator, make sure TE0950_basic_hello is selected and click Build

Finally we will run the application through JTAG. The following steps assume the following switch configuration on the TE0950:

• S2 [1:3] - [OFF, OFF, OFF] - JTAG Boot
• S4 [1:3] - [OFF, ON, OFF] - Only the Versal device in the chain

The board also needs to be connected to a PC using a USB cable plugged in J2

If the TE0950 is connected locally to the PC running Vitis go directly to step 6. If the board is connected to a remote PC, start from step 1.

1. On the remote PC, get the IP address (make sure you can ping the PC running Vitis)

2. Still on the remote PC, run Vivado HW server (you need to have Vivado or Vivado Lab Edition installed)

3. In Vitis click Vitis > Target Connection...

4. Click on the + icon to add a new target

5. Set a target Name and add the IP address of the Host. If the board is connected and Powered ON, you should see the xcve2302 device listed under Advanced. Click OK to confirm the settings

6. In the flow navigator, click on the configuration icon which appears when you hover the right side of the Run line with your mouse

Make sure the Target Connection is set to the remote one you have configured in step 1 to 5 if the board is connected remotely. If the board is connected on the machine running Vitis, just set the setting to local

Open a UART terminal (for example Tera Term) can connect to the COM port corresponding to the TE0950 board with the following settings:

• Speed: 115200
• Data: 8-bit
• Parity: None
• Stop Bits: 1 bit

In Vitis, click on Run in the Flow navigator

In Tera Term you will see the output from the Versal PLM then the Hello World messages from the application

This means that our CIPS is configured well so we can add more pieces to our project. This will be done in the next project.

The full project can be build from Makefile and is available on my github repository

https://github.com/xflorentw/TE0950_Designs/tree/main/01_TE0950_basic

Disclaimers

• AMD, Versal, and Vitis are trademarks or registered trademarks of Advanced Micro Devices, Inc.
• Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.