VCS³ - Video Controls Sensors Development Platform

Introduction

This project demonstrates how to implement end-to-end video pipelines on an AMD Zynq MPSoC FPGA, focusing on real-world use of MIPI CSI-2 cameras and display interfaces. The goal is to explore practical PS–PL co-design techniques for video capture, processing, and output using both the ARM processing system and FPGA fabric.

Sundance has provided the hardware for this project, enabling the development and validation of complete, reproducible examples that can be extended for custom video and vision applications.

VCS³ 3D Kit Overview

The VCS³ 3D Kit is a self-contained video development platform built around the Sundance VCS³ Core. The kit integrates dual cameras, a display, and a VCS³ RP2040 companion board, making it well suited for evaluating compact, high-performance video processing pipelines.

At the heart of the platform is the VCS³ Core: a small single-board computer featuring an AMD Zynq MPSoC with integrated ARM CPUs and FPGA fabric. Measuring just 30 mm × 50 mm, the VCS³ Core combines high computational capability with a very small footprint, enabling FPGA-accelerated video processing in space-constrained applications.

Related Hackster Projects

Custom DPU-PYNQ Overlay for the Sundance VCS³ Board - Hackster.io

FPGA snake! - Hackster.io

Bringup

For the board bringup, we will show you how to use the board files to rapidly build a Vivado project. This block diagram will contain the processor subsystem and any soft Vivado IP cores. This will mostly be a software and hardware hello world to demonstrate the basic features of the this FPGA/SoC and the perpherials avaiable to this development kit.

Step-by-Step details to follow!

• Use board files or show how to do a custom load

git clone https://github.com/SundanceMultiprocessorTechnology/VCS-3_pub.git

• Add the PS system and use the Board Preset configuration.

• Add a Soft processor and hookup the AXI Timer to the block diagram.

• Generate hardware and export to Vitis. You can use the pre-synthesis for the ARM processors and the bitstream is needed for the soft processor.

• Within Vitis, you will need to set a workspace, then create a Platform using the XSA file and selecting your chosen processor.. The ARM processor using "normal" JTAG and the Coresight STDOUT is the most reliable. For PS UART, you will need to use the Xilinx Virtual Cable on the RP2040, instructions here: https://github.com/SundanceMultiprocessorTechnology/xvc-vcs3-rp2040

• After seting the example of the HelloWorld, you can configure the STDOUT

• Then running the debug execution, then once the system is ready continue execution.

PL Fabric Camera Pipeline

In-progress

PL Fabric Display Pipeline

In-progress

PS Processor Video Pipeline

In-progress

Linux EDF flow with PYNQ

In-progress