Custom DPU-PYNQ Overlay for the Sundance VCS³ Board

Introduction

The target platform used in this project is the VCS³ Development Kit, a compact embedded system based on an AMD Zynq™ SoC that combines integrated ARM CPUs with FPGA fabric. This architecture makes the VCS³ well suited for embedded computing and hardware-accelerated applications.

Official vendor store:
https://store.sundance.com/product/vcs3-dev-kit/

Documentation:

• Application Starters Guide:
  https://store.sundance.com/wp-content/uploads/2023/10/VCS3-Application-Starters-Guide-v1.1.pdf
• Development Kit – Getting Started Guide:
  https://store.sundance.com/wp-content/uploads/2025/01/VCS3-Development-Kit-Getting-Started-Guide.pdf
  

About This Project

This project is about porting and enabling the AMD/Xilinx DPU-PYNQ framework on the Sundance VCS³ board, which is not officially supported by the DPU-PYNQ repository out of the box.

DPU-PYNQ normally provides ready-to-use FPGA overlays that allow deep-learning inference (via Vitis-AI DPU) to run easily from Python/Jupyter notebooks on supported Zynq UltraScale+ platforms. This project extends that ecosystem to the custom Sundance VCS³ board, enabling generation of:

• dpu.bit – FPGA bitstream
• dpu.hwh – hardware handoff metadata
• dpu.xclbin – Vitis acceleration binary
• arch.json - defines specific capabilities and configuration of the DPU and used by Vitis-AI compiler

These files make it possible to run neural-network inference using the pynq_dpu Python package on the VCS³ hardware

Motivation

There were two main motivations:

• Hardware limitationThe Sundance VCS³ board is a powerful Zynq UltraScale+ MPSoC platform, but it is not included in the official list of PYNQ-enabled boards. This prevents users from easily deploying AI workloads using DPU-PYNQ.
• Ease of AI deploymentBy adding VCS³ support, the project allows users to:

- Use Python instead of low-level drivers

- Run inference notebooks

- Rapidly prototype AI applications on custom hardware

In short, the project removes a major usability barrier and makes AI acceleration on VCS³ accessible and reproducible.

How does it work?

The project works in several coordinated steps:

1. Extend the DPU-PYNQ board infrastructure

A new VCS³ board directory is created inside the DPU-PYNQ boards/ folder. This includes:

• A project configuration file (prj_config) describing AXI connectivity and kernel mapping
• A DPU configuration header (dpu_conf.vh) that defines the DPU architecture (compute size, memory usage, DSP usage, power settings, etc.)

This tells Vitis how the DPU should be built for the VCS³ FPGA.

2. Create a Vivado accelerated platform (XSA)

Because DPU-PYNQ requires an accelerated platform, a custom Vivado platform project is built targeting the VCS³ board:

• Zynq UltraScale+ MPSoC configured with board presets
• Multiple clocks for DPU and various IPs in the block design
• AXI master/slave interfaces for DDR access
• Interrupt controller and PL-to-PS IRQ wiring

The completed design is exported as a platform.xsa file, which the DPU-PYNQ uses as the hardware foundation.

3. Package the DPU as a Vitis kernel and generate the FPGA overlay

Using Vitis scripts:

• The DPU RTL is packaged into a kernel object (.xo)
• AXI ports are mapped to the platform memory interfaces
• Kernel metadata is generated for system linking

The v++ linker:

• Integrates the DPU kernel with the VCS³ platform
• Synthesizes, places, and routes the design
• Produces the final dpu.xclbin, dpu.bit, dpu.hwh and the arch.json

This step effectively creates the FPGA overlay used by PYNQ.

Tool Versions:

This project targets Vitis-AI version 3.5, which supports the DPUCZDX8G IP version 4.1 and is compatible with Vivado, Vitis, and PetaLinux 2023.1. The design_contest_3.5 release of the DPU-PYNQ repository supports PYNQ 3.0 and Vitis-AI 3.5.0. This release also includes updates specifically targeting the Kria SOM platforms (KR260 and KV260).

DPU C ZD X8G is used for edge devices. The respective accronyms are explained below;

DPU: Deep Learning Processing Unit

C: CNN applications

ZD: ZYNQ DDR hardware platform

X: DECENT Quantization

8: Quantization bitwidth of 8 bits

G: General purpose design target

1. Extend the DPU-PYNQ board infrastructure

The initial step is to clone the DPU-PYNQ repository and check out the design_contest_3.5 branch using the following command:

git clone --branch design_contest_3.5 --single-branch https://github.com/Xilinx/DPU-PYNQ.git

After cloning, the project folder structure should appear as shown below.

.
├── boards
├── contest_patch.sh
├── host
├── LICENSE
├── MANIFEST.in
├── pynq_dpu
├── pyproject.toml
├── README.md
└── setup.py

Change into the boards subdirectory:

cd DPU-PYNQ/boards

This directory contains board-specific subfolders for various target platforms, along with the check_env.sh script, a Makefile, and a README file.

.
├── check_env.sh
├── DPUCZDX8G
├── gzu_5ev
├── kr260_som
├── kv260_som
├── Makefile
├── pynqzu
├── README.md
├── rfsoc2x2
├── rfsoc4x2
├── TySOM-3A-ZU19EG
├── TySOM-3-ZU7EV
├── Ultra96v1
├── Ultra96v2
├── ultrazed_eg_iocc_production
├── vermeo_t1_mpsoc
├── vermeo_t1_rfsoc
├── zcu102
├── zcu104
├── zcu106
├── zcu111
├── zcu1285
├── zcu208
├── zcu216
└── ZUBoard_1CG

Create a directory for the VCS³ board and change into it:

mkdir vcs-3 && cd vcs-3

Create a project configuration file named prj_config in the vcs-3 directory and populate it with the following contents. This file defines the clocking, kernel connectivity, and Vivado implementation strategy used during the Vitis linking process.

# /*
# * Copyright 2019 Xilinx Inc.
# *
# * Licensed under the Apache License, Version 2.0 (the "License");
# * you may not use this file except in compliance with the License.
# * You may obtain a copy of the License at
# *
# *    http://www.apache.org/licenses/LICENSE-2.0
# *
# * Unless required by applicable law or agreed to in writing, software
# * distributed under the License is distributed on an "AS IS" BASIS,
# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# * See the License for the specific language governing permissions and
# * limitations under the License.
# */


[clock]


[connectivity]

sp=DPUCZDX8G_1.M_AXI_GP0:HPC0
sp=DPUCZDX8G_1.M_AXI_HP0:HP0
sp=DPUCZDX8G_1.M_AXI_HP2:HP1


nk=DPUCZDX8G:1

[advanced]
misc=:solution_name=link


[vivado]
prop=run.impl_1.strategy=Performance_Explore

Next, a DPU configuration file (dpu_conf.vh) is created to define the architectural parameters of the DPU IP integrated into the Vivado project. This file specifies the hardware characteristics of the DPU, including compute size, memory usage, parallelism, DSP utilization, and power configuration. These parameters directly determine how neural network models are mapped onto the DPU hardware and therefore must be consistent with the models compiled using Vitis-AI.

In this configuration, the DPU is instantiated with a B1152 architecture, providing a balanced trade-off between performance and resource utilization. URAM and DRAM are disabled, indicating that only on-chip BRAM resources are used for feature maps, weights, and biases. The design enables channel augmentation and sets the ALU parallelism to level 2, improving computational throughput while maintaining compatibility with supported models. DSP resources are prioritized by enabling high DSP48 usage, and the design targets an MPSoC-based platform, consistent with the Zynq UltraScale+ architecture of the VCS³ board.

Any modification to architecture-related parameters in this file—such as DPU size, memory configuration, or parallelism—requires regenerating the corresponding arch.json file and recompiling the neural network models to ensure software–hardware compatibility.

/*
* Copyright 2019 Xilinx Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*    http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

//Setting the arch of DPU, For more details, Please read the PG338 


/*====== Architecture Options ======*/
// |------------------------------------------------------|
// | Support 8 DPU size
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | `define B512               
// +------------------------------------------------------+
// | `define B800                 
// +------------------------------------------------------+
// | `define B1024                 
// +------------------------------------------------------+
// | `define B1152                 
// +------------------------------------------------------+
// | `define B1600                 
// +------------------------------------------------------+
// | `define B2304                 
// +------------------------------------------------------+
// | `define B3136                 
// +------------------------------------------------------+
// | `define B4096                 
// |------------------------------------------------------|

`define B1152 

// |------------------------------------------------------|
// | If the FPGA has Uram. You can define URAM_EN parameter               
// | if change, Don't need update model
// +------------------------------------------------------+
// | for zcu104 : `define URAM_ENABLE               
// +------------------------------------------------------+
// | for zcu102 : `define URAM_DISABLE                 
// |------------------------------------------------------|

`define URAM_DISABLE 

//config URAM
`ifdef URAM_ENABLE
    `define def_UBANK_IMG_N          5
    `define def_UBANK_WGT_N          17
    `define def_UBANK_BIAS           1
`elsif URAM_DISABLE
    `define def_UBANK_IMG_N          0
    `define def_UBANK_WGT_N          0
    `define def_UBANK_BIAS           0
`endif

// |------------------------------------------------------|
// | You can use DRAM if FPGA has extra LUTs               
// | if change, Don't need update model
// +------------------------------------------------------+
// | Enable DRAM  : `define DRAM_ENABLE               
// +------------------------------------------------------+
// | Disable DRAM : `define DRAM_DISABLE                 
// |------------------------------------------------------|

`define DRAM_DISABLE 

//config DRAM
`ifdef DRAM_ENABLE
    `define def_DBANK_IMG_N          1 
    `define def_DBANK_WGT_N          1
    `define def_DBANK_BIAS           1
`elsif DRAM_DISABLE
    `define def_DBANK_IMG_N          0
    `define def_DBANK_WGT_N          0
    `define def_DBANK_BIAS           0
`endif

// |------------------------------------------------------|
// | RAM Usage Configuration              
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | RAM Usage High : `define RAM_USAGE_HIGH               
// +------------------------------------------------------+
// | RAM Usage Low  : `define RAM_USAGE_LOW                 
// |------------------------------------------------------|

`define RAM_USAGE_LOW

// |------------------------------------------------------|
// | Channel Augmentation Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | Enable  : `define CHANNEL_AUGMENTATION_ENABLE              
// +------------------------------------------------------+
// | Disable : `define CHANNEL_AUGMENTATION_DISABLE                
// |------------------------------------------------------|

`define CHANNEL_AUGMENTATION_ENABLE

// |------------------------------------------------------|
// | ALU parallel Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | setting 0  : `define ALU_PARALLEL_DEFAULT              
// +------------------------------------------------------+
// | setting 1  : `define ALU_PARALLEL_1                
// |------------------------------------------------------|
// | setting 2  : `define ALU_PARALLEL_2                
// |------------------------------------------------------|
// | setting 3  : `define ALU_PARALLEL_4                
// |------------------------------------------------------|
// | setting 4  : `define ALU_PARALLEL_8                
// |------------------------------------------------------|

`define ALU_PARALLEL_2 

// +------------------------------------------------------+
// | CONV RELU Type Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | `define CONV_RELU_RELU6
// +------------------------------------------------------+
// | `define CONV_RELU_LEAKYRELU_RELU6
// |------------------------------------------------------|

`define CONV_RELU_LEAKYRELU_RELU6

// +------------------------------------------------------+
// | ALU RELU Type Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | `define ALU_RELU_RELU6
// +------------------------------------------------------+
// | `define ALU_RELU_LEAKYRELU_RELU6
// |------------------------------------------------------|

`define ALU_RELU_RELU6

// |------------------------------------------------------|
// | argmax or max Configuration
// | It relates to model. if change, must update model
// +------------------------------------------------------+
// | enable  : `define SAVE_ARGMAX_ENABLE                 
// +------------------------------------------------------+
// | disable : `define SAVE_ARGMAX_DISABLE                 
// |------------------------------------------------------|

`define SAVE_ARGMAX_ENABLE                
 
// |------------------------------------------------------|
// | DSP48 Usage Configuration  
// | Use dsp replace of lut in conv operate 
// | if change, Don't need update model
// +------------------------------------------------------+
// | `define DSP48_USAGE_HIGH              
// +------------------------------------------------------+
// | `define DSP48_USAGE_LOW                
// |------------------------------------------------------|

`define DSP48_USAGE_HIGH 

// |------------------------------------------------------|
// | Power Configuration
// | if change, Don't need update model
// +------------------------------------------------------+
// | `define LOWPOWER_ENABLE              
// +------------------------------------------------------+
// | `define LOWPOWER_DISABLE               
// |------------------------------------------------------|

`define LOWPOWER_DISABLE

// |------------------------------------------------------|
// | DEVICE Configuration
// | if change, Don't need update model
// +------------------------------------------------------+
// | `define MPSOC              
// +------------------------------------------------------+
// | `define ZYNQ7000               
// |------------------------------------------------------|

`define MPSOC

2. Create a Vivado accelerated platform (XSA)

An AMD XSA (Xilinx Shell Archive) file is required to describe the hardware platform details of the custom Sundance VCS³ board. This file captures the board’s hardware configuration and serves as the input platform definition for Vivado and Vitis during accelerated application and DPU overlay generation.

Before creating the platform project, the Sundance board definition files must be made available to Vivado.

Copy Board Files

Clone the repository below to access the Sundance VCS³ board files.

git clone https://github.com/kwame-debug/vcs3.git

Copy the Sundance VCS³ board files to <vivado installation path>/Xilinx/Vivado/2023.1/boards/

cp -r board_files /tools/Xilinx/Vivado/2023.1/data/boards/

This step enables Vivado to recognize the VCS³ board as a selectable target during project creation.

Launch Vivado

Source the Vivado environment and launch the Vivado workspace by executing the following commands in a Linux terminal:

source /tools/Xilinx/Vivado/2023.1/settings64.sh
vivado &

This command initializes the Vivado environment and opens the Vivado GUI.

Create the Vivado Platform Project

When creating the project:

• Select RTL Project as the project type.
• Ensure that the “Project is an extensible Vitis platform” option is enabled. This option is required to generate a platform compatible with the Vitis acceleration flow.

Select Target Board

Choose VCS-3 from the Boards list, then click Next followed by Finish.

Note: The VCS³ board will only appear in the list if the board files have been copied into the Vivado installation directory as described in the previous step.

Create the Block Design

Create a new block design from the Vivado Flow Navigator.

Add Zynq UltraScale+ MPSoC IP

Add the Zynq UltraScale+ MPSoC IP to the block design.

Apply Board Preset

Click Run Block Automation to apply the VCS³ board preset to the Processing System.Ensure the following options are selected:

• All Automation
• zynq_ultra_ps_e_0
• Apply Board Preset

Click OK to continue.

Add Clock Wizard

Add a Clock Wizard IP and configure three output clocks as follows:

• clk_out_REG_100MHz: 100 MHz
• clk_out_DPU_200MHz: 200 MHz
• clk_out_DSP_400MHz: 400 MHz

Ensure that Active Low Reset and Locked options are enabled. Click OK to close the Clock Wizard.

Add and Configure System Resets

Add three Processor System Reset IPs to the design and rename them as follows:

• proc_sys_reset_100MHz
• proc_sys_reset_200MHz
• proc_sys_reset_400MHz

Connect Clocks and Resets

Use Run Connection Automation to connect the clocks and reset modules:

• Click on the Run Connection Automation link to open the wizard.
• Set clk_in1 of clk_wiz_0 to zynq_ultra_ps_e_0/pl_clk0 (99 MHz)

• Assign reset clock sources:proc_sys_reset_100MHz → /clk_wiz_0/clk_out_REG_100MHzproc_sys_reset_200MHz → /clk_wiz_0/clk_out_DPU_200MHzproc_sys_reset_400MHz → /clk_wiz_0/clk_out_DSP_400MHz

• Set ext_reset_in for all reset modules to /zynq_ultra_ps_e_0/pl_resetn0

Repeat the configuration in the above image for ext_reset_in under proc_sys_reset_200MHz and proc_sys_reset_400MHz.

The figure below shows the final output of the fully configured block design. Different colors are used to highlight the respect clock and reset connections.

Finalize Clock Configuration

• Connect all dcm_locked pins to the Clock Wizard locked output.
• Open Windows → Platform Setup, navigate to Clock Settings, and enable all three clocks.
• Set clk_out_DPU_200MHz as the default clock for kernel linking. The default clock(clk_out_DPU_200MHz) is used during the v++ linker to connect to IP blocks with no user assignments for link configuration.

Add Interrupt Support

Enable interrupt support by:

• Opening the Zynq UltraScale+ MPSoC configuration

• Enabling AXI HPM0 LPD (32-bit data width)

Note: Ensure that AXI HPM0 FPD and AXI HPM1 FPD are disabled.

• Enabling PL-to-PS IRQ0[0–7]

• Adding an AXI Interrupt Controller

• Configuring the interrupt controller for single interrupt output

Double click the Interrupt controller and select “single“ as option for interrupt output Connection as indicated in the figure below and click OK to close the window.

• Connecting axi_intc_0/irq to pl_ps_irq0[0:0]

Click on Run Connection Automation link to open the Run Connection Automation window. Ensure that axi_intc_0 and s_axi are both selected. Select /clk_wiz_0/clk_out_DPU_200MHz as clock source for Master interface and click OK to close the window.

Enable interrupt signals for the platform

Enable AXI Interfaces

Enable AXI master and slave interfaces to allow kernel access to DDR memory:

• Enable required AXI ports in the Processing System (zynq_ultra_ps_e_0)

• Enable M01_AXI through M07_AXI under ps8_0_axi_periph

Note: Ensure that memport for S_AXI_HPC0_FPD and S_AXI_HPC1_FPD are set to S_AXI_HP memport. Leave Memory column blank.

Click on the Platform Name option under Settings and enter the platform details as illustrated below;

Finalize and Validate Design

• Validate the design by pressing F6 (any critical warning shown can be safely ignored)Note: The critical message indicated below shows up. This can be safely ignored by clicking on OK.

• Create the HDL wrapper (select Let Vivado manage wrapper and auto-update)

Right-click on vcs3_bd.bd under Design Sources and select Create HDL Wrapper. Mantain the “Let Vivado manage wrapper and auto-update“ option and click OK.

• Generate the block design (select Global synthesis)Click on Generate block design from flow navigator (under IP INTEGRATOR). Ensure that Global is selected as Synthesis Option.

• Generate the bitstream

Next, click Generate Bitstream in Flow Navigator to launch Runs and Click OK to close the window.

Export Hardware Platform

Export the hardware platform with the following options:

• Platform Type: Hardware and Hardware Emulation
• Platform State: Pre-synthesis
• Include Bitstream: Enabled

After successful bitstream generation, export Hardware Platform and ensure that "Hardware and hardware emulation" is selected as platform type.

As platform state, select Pre-synthesis and include bitstream followed by the Next button.

Copy the generated.xsa file into the vcs-3 folder under boards in the DPU-PYNQ repository and rename it platform.xsa.

.
├── dpu_conf.vh
├── platform.xsa
└── prj_config

3. Package the DPU as a Vitis kernel and generate the FPGA overlay

Before building the FPGA overlay, XRT (Xilinx Runtime) must be enabled so the build and runtime tools can correctly interface with the FPGA and manage accelerator kernels.

source /opt/xilinx/xrt/setup.sh

This step configures the environment with the required XRT drivers, libraries, and utilities needed to package the DPU as a Vitis kernel and generate a PYNQ-compatible FPGA overlay.

Next, navigate back to the boards directory and build the overlay:

cd ..
make BOARD=vcs-3

This command packages the DPU into a Vitis kernel and generates the FPGA overlay binaries required for deployment and execution in the DPU-PYNQ environment.

sundance@sundance-Amd-Am5-Workstation:~/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards$ make BOARD=vcs-3
BOARD: vcs-3
VITIS_PLATFORM: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/platform.xsa
bash check_env.sh
wget -O DPUCZDX8G.tar.gz https://www.xilinx.com/bin/public/openDownload?filename=DPUCZDX8G_VAI_v3.0.tar.gz && \
        tar xf DPUCZDX8G.tar.gz && \
mv DPUCZDX8G_VAI_v3.0 DPUCZDX8G && \
rm DPUCZDX8G.tar.gz
--2025-12-20 13:37:16--  https://www.xilinx.com/bin/public/openDownload?filename=DPUCZDX8G_VAI_v3.0.tar.gz
Resolving www.xilinx.com (www.xilinx.com)... 2.23.210.138, 2.23.210.195
Connecting to www.xilinx.com (www.xilinx.com)|2.23.210.138|:443... connected.
HTTP request sent, awaiting response... 301 Moved Permanently
Location: https://download.amd.com/opendownload/xlnx/DPUCZDX8G_VAI_v3.0.tar.gz [following]
--2025-12-20 13:37:16--  https://download.amd.com/opendownload/xlnx/DPUCZDX8G_VAI_v3.0.tar.gz
Resolving download.amd.com (download.amd.com)... 23.215.233.47
Connecting to download.amd.com (download.amd.com)|23.215.233.47|:443... connected.
HTTP request sent, awaiting response... 200 OK
Length: 83014878 (79M) [application/x-gzip]
Saving to: ‘DPUCZDX8G.tar.gz’

DPUCZDX8G.tar.gz           100%[=====================================>]  79.17M  25.8MB/s    in 3.1s    

2025-12-20 13:37:19 (25.8 MB/s) - ‘DPUCZDX8G.tar.gz’ saved [83014878/83014878]

cp -rf /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/DPUCZDX8G/prj/Vitis/kernel_xml/dpu/kernel.xml /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/kernel_xml/dpu/kernel.xml
cp -f /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/DPUCZDX8G/prj/Vitis/scripts/package_dpu_kernel.tcl /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/scripts/package_dpu_kernel.tcl
sed -i 's/set path_to_hdl "..\/..\/dpu_ip"/set path_to_hdl "..\/DPUCZDX8G\/dpu_ip"/' /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/scripts/package_dpu_kernel.tcl
cp -f /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/DPUCZDX8G/prj/Vitis/scripts/gen_dpu_xo.tcl /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/scripts/gen_dpu_xo.tcl
cp -f /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/DPUCZDX8G/prj/Vitis/scripts/bip_proc.tcl /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/scripts/bip_proc.tcl
cd /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3 ;\
/tools/Xilinx/Vivado/2023.1/Vivado/2023.1/bin/vivado -mode batch -source scripts/gen_dpu_xo.tcl -notrace -tclargs binary_container_1/dpu.xo DPUCZDX8G hw vcs-3

****** Vivado v2023.1 (64-bit)
  **** SW Build 3865809 on Sun May  7 15:04:56 MDT 2023
  **** IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
  **** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source scripts/gen_dpu_xo.tcl -notrace
binary_container_1/dpu.xo
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_para.vh" from the top-level HDL file.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.1/Vivado/2023.1/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((4 < 2) ? 4 : 2)" into user parameter "ELEW_PARALLEL".
INFO: [IP_Flow 19-818] Not transferring value dependency attribute "((4 < 2) ? 4 : 2)" into user parameter "ALU_PARALLEL".
WARNING: [IP_Flow 19-11770] Clock interface 'aclk' has no FREQ_HZ parameter.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-11770] Clock interface 'ap_clk_2' has no FREQ_HZ parameter.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.1/Vivado/2023.1/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Sat Dec 20 13:37:27 2025...
cd /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3 ;\
v++ -t hw --platform /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/platform.xsa --save-temps --config /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/prj_config --xp param:compiler.userPostSysLinkOverlayTcl=/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/DPUCZDX8G/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 \
	--log_dir binary_container_1/logs --package.no_image \
	--remote_ip_cache binary_container_1/ip_cache -o /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/tools/Xilinx/Vivado/2023.1/Vitis/2023.1/data/vitis/vpp/optMap.xml'

****** v++ v2023.1 (64-bit)
  **** SW Build 3860322 on 2023-05-04-06:32:48
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
	Reports: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/reports/link
	Log files: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/logs/link
Running Dispatch Server on port: 43787
INFO: [v++ 60-1548] Creating build summary session with primary output /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin.link_summary, at Sat Dec 20 13:37:41 2025
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/reports/link/v++_link_dpu_guidance.html', at Sat Dec 20 13:37:41 2025
INFO: [v++ 60-895]   Target platform: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/platform.xsa
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/platform.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: xilinx_vcs-3_sundance_vcs3_platform_0_0
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [13:37:41] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xo -keep --config /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/syslinkConfig.ini --xpfm /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/platform.xsa --target hw --output_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int --temp_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [13:37:42] build_xd_ip_db started: /tools/Xilinx/Vivado/2023.1/Vitis/2023.1/bin/build_xd_ip_db -ip_search 0  -sds-pf /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/vcs3_dpu_platform.hpfm -clkid 1 -ip /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/iprepo/xilinx_com_RTLKernel_DPUCZDX8G_1_0,DPUCZDX8G -o /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [13:37:43] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 451.969 ; gain = 0.000 ; free physical = 17381 ; free virtual = 42665
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [13:37:43] cfgen started: /tools/Xilinx/Vivado/2023.1/Vitis/2023.1/bin/cfgen  -nk DPUCZDX8G:1 -sp DPUCZDX8G_1.M_AXI_GP0:HPC0 -sp DPUCZDX8G_1.M_AXI_HP0:HP0 -sp DPUCZDX8G_1.M_AXI_HP2:HP1 -dpa_mem_offload false -dmclkid 1 -r /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G, num: 1  {DPUCZDX8G_1}
INFO: [CFGEN 83-0] Port Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP0, sptag: HP0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP2, sptag: HP1
INFO: [SYSTEM_LINK 82-37] [13:37:44] cfgen finished successfully
Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.49 . Memory (MB): peak = 451.969 ; gain = 0.000 ; free physical = 17387 ; free virtual = 42671
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [13:37:44] cf2bd started: /tools/Xilinx/Vivado/2023.1/Vitis/2023.1/bin/cf2bd  --linux --trace_buffer 1024 --input_file /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/_sysl/.xsd --temp_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link --output_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [13:37:45] cf2bd finished successfully
Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.84 . Memory (MB): peak = 451.969 ; gain = 0.000 ; free physical = 17392 ; free virtual = 42680
INFO: [v++ 60-1441] [13:37:45] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 449.574 ; gain = 0.000 ; free physical = 17431 ; free virtual = 42719
INFO: [v++ 60-1443] [13:37:45] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/sdsl.dat -rtd /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/cf2sw.rtd -nofilter /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/cf2sw_full.rtd -xclbin /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/xclbin_orig.xml -o /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:37:45] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.64 . Memory (MB): peak = 449.574 ; gain = 0.000 ; free physical = 17397 ; free virtual = 42686
INFO: [v++ 60-1443] [13:37:45] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:37:45] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 449.574 ; gain = 0.000 ; free physical = 17397 ; free virtual = 42686
INFO: [v++ 60-1443] [13:37:45] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/platform.xsa -s --remote_ip_cache /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/ip_cache --output_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int --log_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/logs/link --report_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/reports/link --config /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/vplConfig.ini -k /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link --no-info --iprepo /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_DPUCZDX8G_1_0 --messageDb /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link/vpl.pb /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link

****** vpl v2023.1 (64-bit)
  **** SW Build 3860322 on 2023-05-04-06:32:48
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: xilinx_vcs-3_sundance_vcs3_platform_0_0
INFO: [VPL 60-1032] Extracting hardware platform to /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/vivado/vpl/.local/hw_platform
[13:37:48] Run vpl: Step create_project: Started
Creating Vivado project.
[13:37:51] Run vpl: Step create_project: Completed
[13:37:51] Run vpl: Step create_bd: Started
[13:37:53] Run vpl: Step create_bd: Completed
[13:37:53] Run vpl: Step update_bd: Started
[13:37:53] Run vpl: Step update_bd: Completed
[13:37:53] Run vpl: Step generate_target: Started
[13:38:04] Run vpl: Step generate_target: Completed
[13:38:04] Run vpl: Step config_hw_runs: Started
[13:38:04] Run vpl: Step config_hw_runs: Completed
[13:38:04] Run vpl: Step synth: Started
[13:38:34] Block-level synthesis in progress, 8 of 11 jobs complete, 3 jobs running.
[13:39:05] Block-level synthesis in progress, 10 of 11 jobs complete, 1 job running.
[13:39:35] Block-level synthesis in progress, 10 of 11 jobs complete, 1 job running.
[13:40:05] Block-level synthesis in progress, 10 of 11 jobs complete, 1 job running.
[13:40:35] Top-level synthesis in progress.
[13:40:41] Run vpl: Step synth: Completed
[13:40:41] Run vpl: Step impl: Started
[13:41:12] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 03m 25s 

[13:41:12] Starting logic optimization..
[13:41:12] Phase 1 Retarget
[13:41:12] Phase 2 Constant propagation
[13:41:12] Phase 3 Sweep
[13:41:12] Phase 4 BUFG optimization
[13:41:42] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 00m 30s 

[13:41:42] Starting logic placement..
[13:41:42] Phase 1 Placer Initialization
[13:41:42] Phase 1.1 Placer Initialization Netlist Sorting
[13:41:42] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[13:41:42] Phase 1.3 Build Placer Netlist Model
[13:41:42] Phase 1.4 Constrain Clocks/Macros
[13:41:42] Phase 2 Global Placement
[13:41:42] Phase 2.1 Floorplanning
[13:41:42] Phase 2.1.1 Partition Driven Placement
[13:41:42] Phase 2.1.1.1 PBP: Partition Driven Placement
[13:41:42] Phase 2.1.1.2 PBP: Clock Region Placement
[13:41:42] Phase 2.1.1.3 PBP: Discrete Incremental
[13:41:42] Phase 2.1.1.4 PBP: Compute Congestion
[13:41:42] Phase 2.1.1.5 PBP: Macro Placement
[13:41:42] Phase 2.1.1.6 PBP: UpdateTiming
[13:41:42] Phase 5 Shift Register Optimization
[13:41:42] Phase 6 Post Processing Netlist
[13:42:12] Phase 2.1.1.7 PBP: Add part constraints
[13:42:12] Phase 2.2 Update Timing before SLR Path Opt
[13:42:12] Phase 2.3 Post-Processing in Floorplanning
[13:42:12] Phase 2.4 Global Placement Core
[13:42:12] Phase 2.4.1 UpdateTiming Before Physical Synthesis
[13:42:12] Phase 2.4.2 Physical Synthesis In Placer
[13:42:12] Phase 3 Detail Placement
[13:42:12] Phase 3.1 Commit Multi Column Macros
[13:42:12] Phase 3.2 Commit Most Macros & LUTRAMs
[13:42:12] Phase 3.3 Small Shape DP
[13:42:12] Phase 3.3.1 Small Shape Clustering
[13:42:12] Phase 3.3.2 Flow Legalize Slice Clusters
[13:42:12] Phase 3.3.3 Slice Area Swap
[13:42:12] Phase 3.3.3.1 Slice Area Swap Initial
[13:42:42] Phase 3.4 Re-assign LUT pins
[13:42:42] Phase 3.5 Pipeline Register Optimization
[13:42:42] Phase 4 Post Placement Optimization and Clean-Up
[13:42:42] Phase 4.1 Post Commit Optimization
[13:42:42] Phase 4.1.1 Post Placement Optimization
[13:42:42] Phase 4.1.1.1 BUFG Insertion
[13:42:42] Phase 1 Physical Synthesis Initialization
[13:42:42] Phase 4.1.1.2 Post Placement Timing Optimization
[13:42:42] Phase 4.2 Post Placement Cleanup
[13:42:42] Phase 4.3 Placer Reporting
[13:42:42] Phase 4.3.1 Print Estimated Congestion
[13:42:42] Phase 4.4 Final Placement Cleanup
[13:42:42] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 01m 00s 

[13:42:42] Starting logic routing..
[13:42:42] Phase 1 Build RT Design
[13:42:42] Phase 2 Router Initialization
[13:42:42] Phase 2.1 Fix Topology Constraints
[13:42:42] Phase 2.2 Pre Route Cleanup
[13:42:42] Phase 2.3 Global Clock Net Routing
[13:43:12] Phase 2.4 Update Timing
[13:43:12] Phase 3 Initial Routing
[13:43:12] Phase 3.1 Global Routing
[13:43:12] Phase 4 Rip-up And Reroute
[13:43:12] Phase 4.1 Global Iteration 0
[13:43:42] Phase 4.2 Global Iteration 1
[13:43:42] Phase 5 Delay and Skew Optimization
[13:43:42] Phase 5.1 Delay CleanUp
[13:43:42] Phase 5.1.1 Update Timing
[13:43:42] Phase 5.1.2 Update Timing
[13:44:12] Creating bitmap...
[13:44:12] Phase 5.2 Clock Skew Optimization
[13:44:12] Phase 6 Post Hold Fix
[13:44:12] Phase 6.1 Hold Fix Iter
[13:44:12] Phase 6.1.1 Update Timing
[13:44:12] Phase 7 Route finalize
[13:44:12] Phase 8 Verifying routed nets
[13:44:12] Phase 9 Depositing Routes
[13:44:12] Phase 10 Resolve XTalk
[13:44:12] Phase 11 Route finalize
[13:44:12] Phase 12 Post Router Timing
[13:44:12] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 01m 30s 

[13:44:12] Starting bitstream generation..
[13:44:12] Phase 13 Post-Route Event Processing
Check VPL, containing 6 checks, has run: 0 errors
[13:44:15] Run vpl: Step impl: Completed
[13:44:15] Writing bitstream ./vcs3_dpu_wrapper.bit...
[13:44:15] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 00m 02s 
[13:44:15] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [13:44:15] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:06:29 . Memory (MB): peak = 449.574 ; gain = 0.000 ; free physical = 20090 ; free virtual = 43164
INFO: [v++ 60-1443] [13:44:15] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/address_map.xml -sdsl /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/sdsl.dat -xclbin /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/xclbin_orig.xml -rtd /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu.rtd -o /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu.xml
INFO: [v++ 60-1652] Cf2sw returned exit code: 0
INFO: [v++ 60-1441] [13:44:15] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.64 . Memory (MB): peak = 449.574 ; gain = 0.000 ; free physical = 20079 ; free virtual = 43153
INFO: [v++ 60-1443] [13:44:15] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/system.bit --force --target hw --key-value SYS:dfx_enable:false --add-section :JSON:/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu_xml.rtd --add-section BUILD_METADATA:JSON:/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu_build.rtd --add-section EMBEDDED_METADATA:RAW:/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu.xml --add-section SYSTEM_METADATA:RAW:/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx_vcs-3_sundance_vcs3_platform_0_0 --output /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin
INFO: [v++ 60-1454] Run Directory: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link
XRT Build Version: 2.14.354 (2022.2)
       Build Date: 2022-10-08 09:49:53
          Hash ID: 43926231f7183688add2dccfd391b36a1f000bea
Creating a default 'in-memory' xclbin image.

Section: 'BITSTREAM'(0) was successfully added.
Size   : 5568789 bytes
Format : RAW
File   : '/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/system.bit'

Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File   : 'mem_topology'

Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File   : 'ip_layout'

Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File   : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty.  No data in the given JSON file.

Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty.  No action taken.
Format : JSON
File   : '/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu_xml.rtd'

Section: 'BUILD_METADATA'(14) was successfully added.
Size   : 4594 bytes
Format : JSON
File   : '/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu_build.rtd'

Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size   : 4540 bytes
Format : RAW
File   : '/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/dpu.xml'

Section: 'SYSTEM_METADATA'(22) was successfully added.
Size   : 18512 bytes
Format : RAW
File   : '/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (5607918 bytes) to the output file: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [13:44:15] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 449.574 ; gain = 0.000 ; free physical = 20065 ; free virtual = 43144
INFO: [v++ 60-1443] [13:44:15] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --force --info /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin.info --input /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin
INFO: [v++ 60-1454] Run Directory: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link
INFO: [v++ 60-1441] [13:44:16] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 449.574 ; gain = 0.000 ; free physical = 20054 ; free virtual = 43134
INFO: [v++ 60-1443] [13:44:16] Run run_link: Step generate_sc_driver: Started
INFO: [v++ 60-1453] Command Line: 
INFO: [v++ 60-1454] Run Directory: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/run_link
INFO: [v++ 60-2442] Software platform is not available, OS name is set from advanced.param 'software.os': linux
INFO: [v++ 60-2442] Software platform is not available, CPU type is set internally based on part name and design intent from hardware platform: cortex-a53
INFO: [v++ 60-1441] [13:44:16] Run run_link: Step generate_sc_driver: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 449.574 ; gain = 0.000 ; free physical = 20054 ; free virtual = 43134
Check POST-VPL, containing 1 checks, has run: 0 errors
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/reports/link/system_estimate_dpu.xtxt
INFO: [v++ 60-2397] Platform default or user specified output type sd_card detected but is not a supported output for v++ --link. Use the v++ --package option instead to create SD card output.
INFO: [v++ 60-586] Created /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
	Guidance: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/reports/link/v++_link_dpu_guidance.html
	Timing Report: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/reports/link/imp/impl_1_vcs3_dpu_wrapper_timing_summary_routed.rpt
	Vivado Log: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/logs/link/vivado.log
	Steps Log File: /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/logs/link/link.steps.log

INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin.link_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 6m 44s
INFO: [v++ 60-1653] Closing dispatch client.
cp -f /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/vivado/vpl/prj/prj.gen/sources_1/bd/*/hw_handoff/*.hwh \
	/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu.hwh
cp -f /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/link/vivado/vpl/prj/prj.runs/impl_1/*.bit \
	/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu.bit
cp -f /home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/binary_container_1/dpu.xclbin \
	/home/sundance/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards/vcs-3/dpu.xclbin
sundance@sundance-Amd-Am5-Workstation:~/sundance/VCS-3/vcs_base/VCS_3_DPU/DPU-PYNQv3.5/DPU-PYNQ/boards$

The Overlay binaries can be found in the boards/vcs-3 folder after a successful build.

├── binary_container_1
├── dpu.bit
├── dpu_conf.vh
├── dpu.hwh
├── dpu.xclbin
├── kernel_xml
├── packaged_kernel_DPUCZDX8G_hw_vcs-3
├── platform.xsa
├── prj_config
├── sample_link.ini
├── scripts
├── tmp_kernel_pack_DPUCZDX8G_hw_vcs-3
├── vivado.jou
├── vivado.log
└── xcd.log

The arch.json file is located in the path below

./vcs-3/binary_container_1/link/vivado/vpl/prj/prj.gen/sources_1/bd/vcs3_bd/ip/vcs3_bd_DPUCZDX8G_1_0/arch.json

Project Summary

This project extends the DPU-PYNQ framework to support the Sundance VCS³ board, a Zynq UltraScale+ MPSoC platform that is not natively supported by the official PYNQ board list. The goal is to enable Vitis-AI DPU acceleration on the VCS³ board and allow users to run deep-learning inference directly from Python and Jupyter notebooks using the pynq_dpu package.

The project targets Vitis-AI version 3.5, which supports the DPUCZDX8G IP (v4.1) and is compatible with Vivado, Vitis, and PetaLinux 2023.1. Development is based on the design_contest_3.5 branch of the DPU-PYNQ repository, which provides updated infrastructure for recent platforms such as the Kria KR260 and KV260 SOMs.

To achieve this, a custom accelerated Vitis platform was created for the VCS³ board using Vivado. The platform integrates the Zynq UltraScale+ Processing System, clocking and reset infrastructure, AXI interconnects, interrupt support, and DDR memory access required by the DPU. The platform is exported as a Xilinx Shell Archive (XSA) and used by Vitis during kernel linking.

The DPUCZDX8G IP is configured using a custom dpu_conf.vh file, which defines the DPU architecture, including compute size, memory usage, parallelism, DSP utilization, and power configuration. From this hardware configuration, an arch.json file is generated, which accurately describes the DPU architecture to the Vitis-AI compiler. This file is essential for compiling neural-network models that are fully compatible with the hardware DPU implementation.

Using the custom platform, DPU configuration, and architecture description, the Vitis build flow generates the required overlay binaries (dpu.bit, dpu.hwh, and dpu.xclbin). These binaries can be deployed on the VCS³ board and used with the pynq_dpu runtime to execute Vitis-AI–compiled models from Python.

Overall, this project demonstrates how a non-standard Zynq UltraScale+ board can be successfully integrated into the DPU-PYNQ ecosystem, enabling accessible and high-performance AI acceleration on custom hardware