Published © Apache-2.0

Acceleration of Binary Neural Networks using Xilinx FPGA

Exploit Xilinx FPGA's hardware to train neuroevolved binary neural networks, then solve Reinforcement Learning problems (like Atari Games).

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Things used in this project

Hardware components

Xilinx Alveo U50
This project was tested on Alveo U50, however it could be compiled to execute on other Xilinx boards like U250, U280; even in the Cloud (Nimbix or AWS FPGA instances)

Software apps and online services

Ubuntu 18.04
Make sure the Ubuntu version matches Vitis supported list of OS, at the time of this writing, that was Ubuntu 18.04.03
Xilinx Vitis
This is the unified software platform used to compile the code into a bitstream, then that bitstream is used to reconfigure the FPGA using OpenCL runtime.
Xilinx Runtime XRT 2020.1.1
This is the Runtime necessary to communicate with the Alveo U50 via the PCI-Express port.


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v1 - 1 CU Binary

System diagram of the 1CU with binary neurons using only 1.81% of the LookUp Tables in the FPGA.

v2 - 8 CU Binary

Vitis analyzer screenshot of creating a bitstream with 8 CU and binary neurons.

v3 - 8 CU Binary, 3 HBM

Vitis analyzer screenshot of creating a bitstream with 8 CU, binary neurons and 3 HBM banks assigned to each kernel variable.

v4 - 8 CU Binary

Vitis Analyzer report of the XCLBin bitstream of the compiled kernel that has 8 BiSUNA compute units, each with 3 pointer inputs and having direct connection to the HBM memory banks. Each CU uses only 15K LUTs (1.8%), which would be the schematic of a future work v4.


BiSUNA U50 Repository

Repository with the source code needed to recompile two binaries: the BiSUNA executable and the XCLBIN bitstream, both used to reconfigure the FPGA. Also, it contains the configuration files to run the example Mountain Car Reinforcement Learning Environment.




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