Wait! What? I can't get 4K Video Output from KR260?

Overview

Even though KV260 and KR260 are based on the same Kria K26 SoM FPGA, their carrier cards are built differently, which is the primary factor that sets them apart from each other.

They have different built-in interfaces to serve different purposes in the field of application. You can see their interface overview in the following picture.

However, this article is going to be focused on the display interface they have. We will see their capability and differences briefly here. You will finally figure out why you were not able to get 4K Video Output from theKR260 display interface.

Yes exactly...

Huh? Who is this?

I am your audience.

Oh, got it. Let's go together.

Note that the display interface you are seeing on KV260 and KR260 is not coming from the FPGA side but from the PS side.

What??...I was continuously scratching my head how to use HDMI TX SS and DP TX SS IP in these K...boards.

Yes, this is true. You cannot use those IPs directly. Before knowing the actual story. We must also have good knowledge of the PS part of this FPGA chip. So, before quickly diving into the PS part of the K26 FPGA, we first have to understand its foundational FPGA architecture. Technically, if you look at the FPGA chip on the K26 board, they are based on the Zynq UltraScale+ MPSoC FPGA architecture. The chip has both PS and PL parts.

Zynq UltraScale+ MPSoC FPGA Interfaces

The Zynq UltraScale+ MPSoC FPGA chip has the following major built-in PS interfaces (not necessarily available or present in all Zynq UltraScale+ MPSoC FPGA boards)

• DDR
• UART
• I2C
• SPI
• SD/SDIO/eMMC
• GPIO
• Ethernet
• USB
• SATA
• DP
• PCIe
• So on...

These interfaces can be utilized as per your application requirements. But we are focused on the display interface. So, we will be hanging around the DP interface.

Wow !! Nice and Clear....I am curious to know about DP interface....

Perfect! Let's see the following diagram to overview the subblocks of the DP interface. This is technically known as the DP Controller.

If you need details on each sub-block, I will make another part of this article in the future. But here we are cracking why KR260 doesn't get 4K Output for your video application.

Ha ha....

PS Transceivers (PS-GTR)

Having the DP Controller alone cannot get you video output. A transceiver is required to stream out DP packets. Apart from PS interfaces, the PS also has Gigabit Transceivers (GTs) for High-Speed data movement.

Who uses it?

Exactly. It is used by a few of the PS interfaces such as

• 2xUSB3.0,
• 4xGigabit Ethernet (GEM),
• 4xPCIe,
• 2xSATA and,
• Needless to say, 2xDP.

Have a look at the following diagram.

PS has four transceivers, named as PS-GTR, with 6.0 Gbps of bandwidth each.

Each PS-GTR makes one GTR lane (also termed as GT lane) with a pair of TX-RX lines. If you use all four interfaces at the same time, you will be able to use only one GT lane for each interface.

So, each GTR lane provides a maximum of 6Gbps bandwidth, right? So, what about if I want to have more bandwidth for a interface?

Your understanding and question are quite right. If you need more bandwidth, you need to use more GT lanes. But the problem is if your one interface occupies two GT lanes, then GT lanes will be insufficient for the remaining three interfaces. You can target the remaining two GT lanes for only two or one interfacess at a time. This can be summarized by the following points.

• Each PCIe can occupy a maximum of 1xGT lanes at a time -- feasible lanes are PCIe0: GT Lane0 -- PCIe1: Lane1 -- PCIe2: Lane2 -- PCle3: Lane3
• Each DP interface can occupy a maximum of 2xGT lanes at at time -- feasible lanes are DP1: lane0, lane2 -- DP0: lane1 and lane3
• Each SATA interface can occupy a maximum of 1xGT lane at a time -- feasible lanes are SATA0: Lane0 or Lane2 -- SATA1: Lane1 or Lane2
• Each USB3.0 interfaces can occupy a maximum of 1xGT lane -- feasible lanes are USB0 3.0: Lane0 or Lane1 or Lane2 -- USB1 3.0: Lane3 only
• Each GEM can occupy a maximum of 1xGT lane -- feasible lanes are GEM0: Lane0 -- GEM1: Lane1 -- GEM2: Lane2 -- GEM3: Lane3

I never know this configuration.

Thanks! The Vivado PS Customization clearly provides you with the selection options.

The following table will provide you good overview further.

HOWEVER!

There is one guy who put us in the biggest limitation, you never know.

Interesting....Who is that?

It's the FPGA board manufacturer/maker.

Hmm

Even though there is a flexibility to choose the GTR lane as per requirement, the board manufacturers might have created their PCB differently. They might have used the GT lane differently. For example, if a board manufacturer has hardwired/tied up GT Lane0 interface pins for USB0 3.0 in their FPGA board, then you cannot assign GTR Lane1 or Lane2 to it. Similarly, if the board maker created a board that hardwired 4xGT Lanes for its 4xPCIe interface, you are unlucky to utilize other PS interfaces.

That's insightsful...We need to get back into our video support

KV260, KR260 DP Interfaces

This is the perfect time to introduce why you cannot achieve 4K video output from the KR260 board. Like I said, the board manufacturers can put us in a limitation. Let's check the DP interface of the KR260 board.

OH...looks like, we only have a single GTR lane tied up. What about KV260?

You are such a fast guy. You quickly picked up. We have the following DP interface from KV260.

We have two GTR lanes tied up

Definitely. The major difference between the KR260 and KV260 DP interface is that KR260 has a single GTR lane, while KV260 has two GTR lanes tied up.

If you are working with DP interface in Vivado Project, you notice that Vivado automatically identifies these configurations when you do "Run Block Automation" for PS.

The following pictures show the GT lane selection for the DP interface in the Vivado PS customization window.

I got your points

Bandwidth Calculation

Let's calculate the video bandwidth for each case. There can be multiple video formats, but I am considering only two relevant video formats.

No problem....I will check that myself.

Perfect! To stream

• Format1: 3840x2160@60Hz, RGB888 --- we need 14.256 Gbps
• Format2: 3840x2160@30Hz, RGB888 --- we need 7.128 Gbps

Let's check the GTR lane bandwidth in

• KV260 -- we have 2xGT lanes -- Resulting Total Lane Bandwidth: 12 Gbps -- Format2 only supported. Insufficient bandwidth for Format1.
• KR260 -- we have 1xGT lane -- Resulting Total Lane Bandwidth: 6 Gbps -- Bandwidth is insufficient for both Format1 and Format2, but lower video formats such as 1920x1080 are supported.

Hmm...I didn't know this. Looks like I get the answer.

Yes. For the above-mentioned video formats, you cannot get 4K output from the KR260 board.

Is there any way to get 4K output?

Interestingly, if you are also a pro FPGA board maker, there are still ways to get 4K video output if your application needs. That is, you can create your own carrier card to have your own interfaces. You can build carrier cards with not only PS DP but also PL DP with improved capabilities. Technically, both boards have the same FPGA chip. If you are focused on the video interface only without needing the KR260 built-in interfaces, you can still go with KV260.

Sounds great!

BONUS! We didn't cover the Gigabit Transceivers that the PL part has. The K260 FPGA SoM is equipped with built-in 4xGTH GTs. Each GT offers a maximum of 16.375 Gbps. You can get a full 4K resolution output.

Conclusion

KR260 and KV260 boards are designed to serve different application domains. KR260 is more focused on the Robotics and Automation domain, while KV260 is more focused on the Vision and Video domain. That's why KR260 has limited video capabilities.

I hope you enjoyed the article with insightful information.

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References

• https://docs.amd.com/r/en-US/ug1089-kv260-starter-kit/Summary
• https://docs.amd.com/r/en-US/ug1092-kr260-starter-kit
• https://docs.amd.com/v/u/en-US/ug1085-zynq-ultrascale-trm
• https://docs.amd.com/v/u/en-US/ug576-ultrascale-gth-transceivers
• https://www.hackster.io/nikilthapa/4k-tpg-video-streaming-in-kria-kv260-baremetal-part-1-c0c9d6