Software apps and online services
Here, I used a bare-metal approach for the 4K TPG Video Pipeline implementation. The board I used is the amazing Kria KV260 Vision AI Starter Kit. I will go through hardware and software design and finally run the design on board.
I have separated this project article into two parts (part 1 and part 2).
In Part 1, I will cover hardware design in vivado while in Part 2, I will cover software design in Vitis and finally the output of design.
The tools I used are
- Vitis Unified Software Platform 2021.1
- Ubuntu 20.04 LTS
Before beginning, I assume you are already familiar with project creation in Vivado. I have skipped most of the steps here. However, we must select the board properly. As the kv260 board has a carrier board, we must connect it with Kria SoM in the following ways.
Vivado IP Integrator(VIPI)
I used VIPI to build the entire video pipeline block. The major IPs we require are listed as follows:
- Zynq UltraScale+ MPSoC Processing System (PS)
- Video Test Pattern Generator (TPG)
- Clocking Wizard
- Video Timing Controller (VTC)
- AXI4-Stream to Video Out
Let’s add all the IPs one by one in VIPI Diagram space and do their customizations and connections.
Zynq UltraScale+ MPSoC PS
Let's first do the Run Block Automation after adding this block in VIPI. It will preset the PS IP according to the board information.
One thing to note is that the KV260 Display Port (DP) is coming out from the PS side, not from the PL side. But here you see the video data is coming from the PL side. How to send this data to DP? Okay, to address this case, we have to enable Live Mode in PS. This will add a parallel video interface in the PS IP block. So, we can connect the PL video interface to the PS video interface.
Let’s follow the steps to enable Live Video Mode in PS.
Open customization window > PS-PL Configuration > General > Others > Live Video > 1
It is a highly configurable IP to fulfill clocking requirements in the design. IP can generate multiple clock outputs while taking up to two clock inputs. You can find more details about this IP in its product guide PG065.
In our design, the IP is configured to generate three clocks as follows:
- clk_out1 - 100MHz for Axilite interface
- clk_300 - 300MHz for AXI Stream
- clk_297 - 297MHz for Video clock
Video Test Pattern Generator (VTPG)
As our pipeline needs a video source, I used Xilinx's VTPG IP. It is also highly customizable. To support 4K resolution, we must have column and row values be 4096 and 2160 respectively. We let other parameters as it is.
Video Timing Controller (VTC)
This IP is responsible for generating as well as detecting the video timing regarding video resolution. Here in this design, we need to generate the video timing. So, IP is customized for a generation.
As we go to the Default/Constant tab, we can select any of three video modes to generate their respective video timing. We can also select custom mode to manually set the video timing for custom resolution.
In our design case, I have enabled the AXI Lite interface so that I can program this IP to generate video timing for 4K resolution.
The timing generation is controlled by Axis2Video for the synchronization between the stream and its timing. So, we need to connect VTC’s gen_clken pin to Axis2Video’s vtg_ce pin.
AXI4-Stream to Video Out (Axis2Video)
This IP takes AXI4 Stream and Video Timing as Input and converts it into Parallel Video. We can then connect this video to the DP video interface in the Zynq PS block. As DP video data width is 36 bit, we also need to set parallel video data width to 36 bit by setting Native Video Output Component Width 12.
We also set clock mode Independent so that we can give separate video clock. We let other parameters as it is.
Let’s expand the Axis2Video’s parallel video interface
Let's connect the pins as follows;
(Axis2Video) (Zynq U+ MPSoC PS)
vid_active video ------> dp_live_video_in_de
vid_data ------> dp_live_video_in_pixel1[35:0]
vid_hsync ------> dp_live_video_in_hsync
vid_vsync ------> dp_live_video_in_vsync
We need to establish the AXI4Stream interface connection between VTPG and Axis2Video IPs to complete a pipeline. Let's connect interface as shown below:
m_axis_video (VTPG) -------> video_in (Axis2Video)
As we are generating three clock outputs from the clock wizard, we need to connect these in the following manner.
Finally, let’s run connection automation to connect all AXI Lite interfaces of IPs to Master AXI Port in the Zynq PS block. Vivado will automatically add AXI Interconnect IP and do the necessary clock and reset pin connection for it.
As you might have noticed the processor System Reset IPs are also automatically added. We need to connect the ext_reset_in pin to the pl_resetn pin of the Zynq PS block.
Let's validate the design and regenerate the layout and our final block design will look like as shown below:
I think you guys have noticed some extra IP blocks in my final block design. I have connected Integrated Logic Analyzer (ILA) blocks to monitor the video stream signals and the locked or underflow status of the output video.
To include such a block in your design, You can right-click on the signal interface or pin and select Debug option. Finally, do the run connection automation so that vivado automatically connects ILA blocks in your desired interface or pin.Bitstream Generation
As the design does not have any external ports, the design does not require any constraints.
Let's first CreateHDL Wrapper
then Generate the bitstream
After bitstream generation, export the hardware design as following the steps.
Vivado Menu > File > Export > Export Hardware > Next > Include bitstream > Next > Set XSA file name > FinishWhat's Next?
Up to here, we completed the hardware design for the 4K TPG Video Pipeline and exported the hardware design. This completes Part 1 of the design. We will move on to Part 2 of the design, where we will create a software application and run the design on the board.