Simulating AI Engine Designs with an RTL Testbench

Introduction

Recently we examined how we could develop Versal based system solutions using Vitis, we have also examined how we can simulate AIE and HLS modules using Python or MATLAB.

In this project we are going to examine how we are able to simulate the Vitis Sub System (VSS) AIE design within Vivado using XSIM.

This completes the development loop, for many applications. Simulation of the AIE using Vitis Analyser or Python / Simulink enables algorithm developers to be able to verify the desired AIE functionality.

Being able to simulate the design in XSIM enables the programmable logic designers to be able to include the AIE functionality within the logic design and verify its integration and functionality with the wider logic design.

This simulation in XSIM does not require QEMU, as used previously in hardware emulation flows. Instead the PS is simulated using the AIE test bench.

This project is based upon the System Design with Vitis and Versal AIE project, as such you will need to first create this project and demonstrate it is working as expected.

This pipe cleans the process and ensures we have the development environment correctly set up for our application.

Getting Started

Having run through the project above, you will notice under the development area several different directories which were created throughout the process.

Under the VSS directory, you will observe several directories including build, src and IP. The one of interest to us for this project is the cosim directory, there are also MATLAB and Python functional simulation directories.

The cosim directory is the one of interest for this project. Under this directory we will see a make file, src directory and document files.

Within the src files directory we will see several system Verilog files, these system Verilog files form the test bench which wraps around the VSS. There are also XSIM waveform configurations and a AIESIM file which also is used in simulation.

The main script within this directory is a TCL script which creates the simulation.

#
# Copyright (C) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: X11
#

## ===================================================================================
## Create a Vivado project for cosimulation
## This script takes in two argument:
## VSS_NAME
## DEVICE_NAME (e.g. xcvc1902-vsva2197-2MP-e-S)
## ===================================================================================
namespace eval _tcl {
  proc get_script_folder {} {
    set script_path [file normalize [info script]]
    set script_folder [file dirname $script_path]
    return $script_folder
  }
}

variable script_folder
set script_folder [_tcl::get_script_folder]

#set_param board.repoPaths ../board_repo/boards/Xilinx/vck190

## WORKAROUND - Hardcode platform and device name as tcl arguments is not passed properly to Vitis
set VSS_NAME [lindex $argv 0]
puts "Creating VSS cosim project for : \"$VSS_NAME\""
set DEVICE_NAME [lindex $argv 1]
puts "Using : \"$DEVICE_NAME\""
set BUILD_DIR build

create_project -f ${VSS_NAME} ${BUILD_DIR}/${VSS_NAME}_cosim -part $DEVICE_NAME
#update_compile_order -fileset sources_1

## ===================================================================================
## Import VSS, create a RTL wrapper for the Vitis Region and add to files
## ===================================================================================
vitis::import_vss ${script_folder}/../../build/${VSS_NAME}/${VSS_NAME}.vss
open_bd_design ${BUILD_DIR}/${VSS_NAME}_cosim/${VSS_NAME}.srcs/sources_1/bd/${VSS_NAME}/${VSS_NAME}.bd
validate_bd_design
save_bd_design
current_bd_design [get_bd_designs ${VSS_NAME}]
make_wrapper -files [get_files ${BUILD_DIR}/${VSS_NAME}_cosim/${VSS_NAME}.srcs/sources_1/bd/${VSS_NAME}/${VSS_NAME}.bd] -top
add_files -norecurse ${BUILD_DIR}/${VSS_NAME}_cosim/${VSS_NAME}.gen/sources_1/bd/${VSS_NAME}/hdl/${VSS_NAME}_wrapper.v
update_compile_order -fileset sources_1

## ===================================================================================
## Add testbench
## ===================================================================================
#break
add_files -fileset sim_1 -norecurse ${script_folder}/driver_axis.sv
add_files -fileset sim_1 -norecurse ${script_folder}/monitor_axis.sv
add_files -fileset sim_1 -norecurse ${script_folder}/testbench.sv
set_property top tb_top [get_filesets sim_1]
update_compile_order -fileset sim_1

## ===================================================================================
## Setup simulation
## ===================================================================================
#set_property generate_scripts_only 1 [current_fileset -simset]
set_property -name {xsim.simulate.runtime} -value {0us} -objects [get_filesets sim_1]
set_property -name {xsim.simulate.xsim.more_options} -value {-testplusarg VERBOSITY_FATAL_TO_WARN} -objects [get_filesets sim_1]
set_property -name {xsim.elaborate.xelab.more_options} -value {-debug sc} -objects [get_filesets sim_1]

## ===================================================================================
## Launch simulation
## ===================================================================================
launch_simulation
open_wave_config ${script_folder}/tb_top_behav.wcfg
open_wave_config ${script_folder}/datamovers.wcfg
open_wave_config ${script_folder}/datamovers2.wcfg
open_wave_config ${script_folder}/fir_filters.wcfg
log_wave -r *
run 5us

The make file within the cosim directory, contains all of the necessary, environment settings and variables for the project such as target board etc.

#
# Copyright (C) 2023-2025, Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: X11
#

# =========================================================
# Part and DUT setup
# =========================================================
VSS             ?= vss_top
PART            ?= xcvc1902-vsva2197-2MP-e-S

# =========================================================
# BUILD PRODUCTS
# ========================================================
BUILD_DIR := build
SIM_DIR   := $(BUILD_DIR)/$(VSS)_cosim/$(VSS).sim/sim_1/behav/xsim

# =========================================================
# SOURCE DIRECTORIES
# =========================================================
SRC_DIR := src

# =========================================================
# Paths needed by xsim
# =========================================================
export AIE_WORK_DIR :=$(AIE_WORK)
export ENABLE_AIE_DBG_TRACE=true
export AIESIM_OPTIONS=$(shell pwd)/$(SRC_DIR)/aiesim.txt
#export LD_LIBRARY_PATH :=$(XILINX_VITIS)/aietools/lib/lnx64.o:$(LD_LIBRARY_PATH)

# =========================================================
# Testbench project script
# =========================================================
COSIM_TCL       := $(SRC_DIR)/cosim_proj.tcl


# =========================================================
# DEPENDENCIES
# =========================================================
DEPS_VSS     := ../build/$(VSS)/$(VSS).vss
DEPS_COSIM   := $(SRC_DIR)/cosim_proj.tcl
DEPS_COSIM   += $(wildcard ${SRC_DIR}/*.sv)

# =========================================================
# Recipes
# =========================================================
crts: $(AIE_WORK_DIR)
	cd $(AIE_WORK_DIR)/ps/c_rts/systemC && \
	$(MAKE) -f Makefile.xsim

cosim_vss: crts $(DEPS_VSS) $(DEPS_COSIM)
	vivado -source $(COSIM_TCL) -tclargs $(VSS) $(PART)

clean:
	rm -rf $(BUILD_DIR)
	rm -rf .Xil vivado* .crash*

The simulation uses both the AIE simulator and XSIM interchanging control / data by use of System C and VCD.

Just like any other programmable logic simulation we need to create a test benches to wrap around the unit under test.

The TCL file creates a Vivado project and import the VSS created earlier in the project flow.

This will create a IP integrator block diagram which contains the AIE engine along with supporting features.

To create the project and run the simulation, from the base directory of the project run the command.

make vss_cosim -C vss

Once the script completes you will see Vivado open with the completed simulation waveforms displayed.

Under the design sources you will be able to see the AIEPRJ added as part of the VSS import.

Opening the IP Integrator block diagram you will see the configured AI Engine.

As part of the project creation you will also see the project has several test bench files added to the project.

Running the make file will automatically run the simulation for 5 microseconds, leaving Vivado showing the simulation perspective.

Under the scope you will be able to see the hierarchy, beneath the DUT and VSS Top you will be able to see the AI Engine which is defined as a System C module.

Having run the simulation you will be able to see several waveforms, each one has been configured to show part of the design in detail.

The first waveform shows the top level of the simulation.

The second element shows the output from the DSP Filters.

The third and fourth waveforms show the data movers.

These simulations show the performance of the the logic design with the AIE included. We might also want to examine the AIE performance within the Vitis Simulator, which was also run as part of this simulation.

To do so we can open the Vitis Simulator, and examine the results from its simulation, which give a different perspective.

We can open the Vitis analyser with the following command.

vitis_analyzer ./vss/cosim/build/vss_top_cosim/vss_top.sim/sim_1/behav/xsim/default.aierun_summary

Upon opening the VItis Analyser we will see the status of the AI Engine run being completed.

We can then observe the graph which shows how the AIE software is designed and implemented. This was originally created in Vitis during the initial project.

It is also possible to see the physical implementation of the graph within the array of AI engine tiles in the target device.

We are also able to observe the trace to examine the sequence of operations.

We can also take a detailed look into the performance metrics of different elements of the graph.

Wrap Up

This project has shown how we are able to take a previously created Vitis Sub System and create a Vivado project such that the AIE can be simulated as part of the larger logic design.

We are also able to examine the AIE Graph performance using Vitis Analyser. While Vitis Functional Simulation enables AI and SW developers to be able to verify the performance of their algorithms. Vivado simulation of the AIE design enables programmable logic designers the ability to simulate the wider design including the AIE.

Links

If you want to try similar the following links might be of interest.

• Overview • AI Engine Tools and Flows User Guide (UG1076) • Reader • AMD Technical Information Portal
• Overview • Versal Adaptive SoC AI Engine Architecture Manual (AM009) • Reader • AMD Technical Information Portal
• AI Engine Kernel and Graph Programming Guide