System Design with Vitis and Versal AIE

Introduction

Recently we examined how we could develop an AMD SoC solution using the Vitis Unified heterogeneous system flow. This project targeted a UltraScale+ Zynq MPSoC running on a Tira ZUBoard.

In this project we are going to examine how we can leverage the Vitis Unified heterogeneous system design flow when working with Versal Devices.

This flow provides all the benefits we saw in the previous project, but also brings several new capabilities and features. Of course the benefit is it enables us when targeting Versal devices which contain AIE, AIE-ML or AIE-ML V2 to be able to leverage then for not only AI / ML applications but also Digital Signal Processing applications as well.

For this project I will be using Vitis and Vivado 2025.1 and I will targeting the VCK190 development board. However, as we will be starting from scratch with platform development etc you can follow along with any Versal development board.

To get started with this project you will also need to ensure your development machine also contains PetaLinux 2025.1 and the system root.

Creating this application will consist of several stages.

• Create a Vitis Sub System (VSS) component - this will contain some custom RTL, HLS and the AIE.
• Create a Vivado Extensible Platform
• Compile the VSS to create a Vitis Metadata Archive (VMA) to enable it to be imported into Vivado for final performance optimisation
• Create the Linux applications and run on the hardware.

For this application we are going to leverage the AMD reference design on creating a Versal Custom Platform Integration using Vitis Subsystem. This is available on the AMD GitHub.

As such the first thing we need to do is clone this repo as it will provide many of the source files and scripts that we need for the application.

Throughout this project we are going to examine several concepts such as the Vitis Sub System, Vitis Meta Archive, Extensible Platforms and Fixed Platforms.

These concepts are illustrated in the image below.

Overview

This project will consist of several steps, a summary of these steps is presented below.

• Set up environment – Install Vivado, Vitis, and PetaLinux; get the board (e.g. VCK190) and reference design files.
• Create Vivado platform – Build a Vivado design with PS, NoC, AIE, and AXI interfaces that Vitis can target.
• Create and Integrate a Vitis Subsystem (VSS) – create the RTL, HLS, and AIE kernels.
• Integrate VSS with Vivado Design - Reflect the Vitis Subsystem into the Vivado platform.
• Create Vitis Platform – Create the fixed Vitis platform.
• Build PS Application (Processing System) - Use Vitis to create the PS application.
• Package to SD card - Create the deployable image.
• Test: Run on VCK190 Evaluation Kit and verify functionality with test apps

Licensing

To be able to create this tutorial we need to have the correct licenses install in Vivado. Using the Vivado license manager ensure select the 2025 AI Engine Tools License and Vitis HLS License. Select either node locked or floating as you need for your system.

Once this is completed you will be able to see Vitis_HLS and several AIE options within the licnese status.

With these installed we are ready to get going.

Vivado Platform

The first step in the development of this project is to create the Vivado platform which is used as the platform for Vitis. Using the scripts from the git repo we can create the hardware platform for us to explore.

While for this project we are creating the platform as part of the tutorial, Vivado provides a Customisable Example Design (CED) template which can be used for a quick start. no

This platform will provide the clocks, resets, AXI interfaces and interrupts made available for Vitis to use. It will also include elements in the Versal system we need to create the solution including AIE, CIPS and NoC.

We can build the application by running the make file, however first we need to set up the environment.

Within the terminal source the settings64 script under the Vitis installation directory.

source <Vitis_Installation_Path>/settings64.sh

Change directory to the tutorial folder, this is the example we will be using for the project the 02-Versal_Vitis_Subsystem_Flow

Vitis-Tutorials/Vitis_System_Design/Design_Tutorials/02-Versal_Vitis_Subsystem_Flow

To get started and create the base Vivado platform we can use the command

make vivado_platform

After a few minutes the script will complete and the base platform will be created. We can open the project which has been created in Vivado and we will see a basic design.

This design provides the basic platform to which Vitis using its heterogeneous system capabilities can add too. If you read the previous project, you will notice the provision of clocks, resets, the CIPS and NoC configured and connected to the DDR4 and LPDDR4 along with the instantiation of the AIE Engines connected to the NoC.

Like the CIPS the AIE engines are hard features in the silicon, similar to the CIPS however, we can configure its interfacing and application. Unlike CIPS however we do not do this using a dialog box in Vivado but using Vitis.

However, before we do that lets explore the platform a little more.

Double clicking on the AI Engine block will provide some basic clocking settings. The dialog clearly states further configuration is performed by the Vitis Linker which we will see later.

The Vitis linker needs to know what resources are available, it uses these resources to connect to the HLS, RTL and AIE Kernels.

Examining the platform setup will show the AXI interfaces, clocks, interrupts and platform information made available as resources.

The first element of this is the AXI, looking at the platform these have been made available from the smart connect.

For clocking, four clocks have been made available to the Vitis linker, these range in frequency from 500MHz to 62.5 MHz.

The final element is the interrupt connections which are available to the Vitis Linker.

The next step is to create a Vitis Sub System.

Vitis Sub System

A Vitis Sub System (VSS) is an element of a design which consists of either RTL, HLS or AIE kernels or any combination. This subsystem can be integrated using the Vitis linker and then pulled back into Vivado using a VMA to fine tune the implementation in Vivado.

While a VSS useful for many projects as it is helpful for sub-system IP management, it is not requirement for the VCK190 development.

For the Vitis subsystem provided in the example design it instantiates three elements.

• AXIS 1 to 2 - HLS IP core which duplicates a AXI Stream in to two.
• Vadd - HLS IP core which adds together two AXI Streams.
• Counter - RTL IP Core which impalements a free running counter.
• AIE - AIE graphs which implement a data mover and two FIR Filters.

We can create the VSS from the repository using the command

make vss

Of course, we might want to take a look at the design and see explore it a little more, as we did with Vivado. One of the main interesting elements is the AIE Simulator and graph we can open the AIE Simulator and Vitis Analyser using the command.

make sim_analyzer -C vss/ip/aie

This will show the predicted throughput of the system

Vitis IP

The VSS contains the elements which we need to integrate with the Vivado design however, there are other elements which sit within the Vitis domain.

This includes the blocks which perform memory mapped to stream and stream to memory mapped modules which enables data to be played through the AIE FIR kernels.

We can compile these elements using the command

make vitis_ip

Once this has been completed the next step is to export the Vitis Metadata Archive (VMA) which we can take back into Vivado.

make vma_export

Once completed we are able to then merge the VMA with the Vivado design and see the updated design.

You might be wondering why we want to go back into Vivado, from Vitis. By taking the design back into Vivado, it users are able to focus on optimizations or change contents outside of the Vitis region.

To do this we run the command

make vivado_fixed

This makes the fixed Vivado platform with everything from the Vitis system design included.

To ensure we can progress on and create the remaining embedded Linux and application stages of the design. This will also synthesise, implement and export the XSA for us to use at a later stage.

Opening Vivado we will now see an updated design with the AIE block showing connections and the new Vitis region.

Closer view of the AIE and Vitis Region.

Within this Vitis region we will see, the HLS and RTL Kernels along with the infrastructure from Vivado IP blocks to connect the design as defined.

Looking at the implementation however we can see we have still a lot of resources remaining for future development.

The final element of this project is to create the embedded Linux OS and Application software.

Vitis Platform

With the fixed XSA available, we are in a position to create the Vitis platform. This platform will contain the hardware and software elements of the design. It is on to this platform the solution will be completed.

To make the platform we can run the command

make vitis_platform

Once the platform is created the next step is to create the PS applications, this application is what will run and exercise the AIE application.

make ps_apps

The final stage of the design is to package the design for deployment, this will provide us with the files we can put onto a SD Card.

make package

Testing

The output of the package stage will result in several files being created which can be copied on to a SD Card.

Once these files have been copied on to the SD Card, we can insert the SD Card into the VCK190 and ensure the device is set to boot from SD.

Powering on the VCK190 will enable the system to boot, after a few seconds you will see a prompt.

Here the user name is petalinux and you will be prompted to set a password as you log in for the first time.

To run the application we need to be root use the command

sudo su

We can then run the application which is located on the SD card. issue the commands.

vck190-versal:/home/petalinux# cd /run/media/mmcblk0p1/
vck190-versal:/run/media/mmcblk0p1# ./aie_dly_test.exe my.xclbin 512

This will run the AIE test application, this application will test the design with 512 samples.

At the end of the process you will see the test results reported as passed.

Wrap Up

This project has demonstrated how we are able to pull together different elements of a Versal system. This system pulls together several different elements, the AIE Graph, RTL and HLS kernels along with showing how Vitis designs can be re imported into Vivado for final optimization and integration.