Add Peripheral Support to Kria KR260 Vivado 2022.1 Project

In my last post, I covered how to create a basic hardware project for the Kria KR260 Robotics Starter kit in Vivado 2022.1 with the hooks for an FPGA/hardware accelerated application to be developed later on in Vitis and ran on it. This post is a follow on to it (using that same Vivado 2022.1 project created in that post) that covers how to add some of the specific hardware hooks for the peripherals on the KR260 carrier board.

As far as I'm aware, the KR260 is only supported in version 2022.1 and on. Unless you're willing to do a lot of manual configuration in the Vivado project since older versions of the board preset files don't exist, I highly recommend upgrading to Vivado 2022.1 or later to use with the Kria KR260.

Enable Hardware in ZynqMP Processing System IP

The main configuration that needs to be done is enabling the respective ports for each peripheral on the Zynq MPSoC chip itself. To do this, open the block design in the Vivado project and double-click on the Zynq UltraScale+ MPSoC IP block to bring up it configuration window.

Start with the I/O Configuration tab, under Low Speed > Memory Interfaces, verify the following QSPI settings (this should have been set automatically when block automation was ran for the Zynq MPSoC IP in the previous post):

Under Low Speed > I/O Peripherals, enable I2C1 on MIO pins 24 - 25. MIO pins are dedicated interface pins on the Zynq MPSoC chips with direct connection to the ARM-cores. These pins are routed to specific packages pins of the chip that are not accessible to the programmable logic of the FPGA and are not changeable, so there is no need for the user to manually map a signal name to pin number in a constraints file.

Verify the PMU settings:

Enable SPI 1 on MIO pins 6 - 11:

Enable UART 1 on MIO pins 36 - 37:

Enable GPIO0 MIO and GPIO1 MIO:

Enable both system-wide watch dog timers SWDT 0 and SWDT 1 under Processing Unit:

Enable all four triple timer counters (TTC0 - TTC3) with the first of which outputting its wave out signal to EMIO:

Next under High Speed for the RJ45 Ethernet ports on the KR260, enable GEM 0 on GT Lane0 and GEM 1 on MIO pins 38 - 49 with its MDIO on MIO pins 50 -51:

Under USB0, enable USB 0 on MIO pins 52 - 63 and USB 3.0 on GT Lane2:

Under USB1, enable USB 1 on MIO pins 64 - 75 and USB 3.0 on GT Lane3:

Configure the reset pins for the USB ports to use a separate MIO pin with an active low polarity. Put USB 0 reset on MIO pin 76 and USB 1 reset on MIO pin 77:

Enable the DisplayPort on MIO pins 27 - 30 with a Single Lower lane selection on GT Lane1:

There is no benefit to enabling the SATA or PCIe peripherals as they are not physically routed to anything on the Kria PCB nor KR260 PCB.

Again, Clock Configuration and DDR Configuration were taken care of by the block automation that was ran for the Zynq MPSoC IP which applied the Kria board presets.

Thus, skip to the PS-PL Configuration tab (PS = Processing System, PL = Programmable Logic). Under General > Fabric Reset Enable, increase Number of Fabric Resets from 1 to 4:

In the end, the block design tab should have check marks on each of the enabled peripherals:

To see how each of these peripherals connect on the KR260 PCB, check out and download its schematic here. There is a very helpful block diagram overview on the second page.

CPU Fan Driver IP in Block Design

To drive the CPU fan on the Kria with the appropriate PWM signal, the wave output of TTC0 is used. Of the 3-bits of the TTC0 wave out signal, only bit 0 is needed.

Add Xslice IP block and configure to take a 3-bit input and output the LSB, bit 0:

Connect the Din input of xslice_0 to emio_ttc0_wave_o of the Zynq MPSoC IP.

Right-click on the Dout pin of xslice_0 and select the option to Make External. This will create a port pin and connect the Dout pin to it automatically. Rename the port to fan_en_b and regenerate the layout.

Validate the block design, save it again, and select Generate Block Design from the Flow Navigator window. Then create a new HDL wrapper, selecting the option to let Vivado auto-manage (see previous post for how to create an HDL wrapper).

CPU Fan Constraints

Since the EMIO pins of the Zynq MPSoc is reconfigurable in terms of what package pin it can be mapped to, a constraint file needs to be created to map the fan_en_b signal to the proper package pin on the chip as expected by the PCB layout of the Kria and KR260.

Create a constraints file by selecting Add Sources from the Flow Navigator window and selecting the Add or create constraints option.

Select the Create File option and give it the desired file name, then click Finish.

Open the newly created constraint file from the Sources window and add the following constraints:

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

#Fan Speed Enable
set_property PACKAGE_PIN A12 [get_ports {fan_en_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {fan_en_b}]
set_property SLEW SLOW [get_ports {fan_en_b}]
set_property DRIVE 4 [get_ports {fan_en_b}]

Finally, save the constraints file.

Export Platform

After running synthesis, implementation, and generating a new bitstream, the hardware needs to be re-exported as a new platform for use in Vitis/PetaLinux later on to write the corresponding software.

Select Export Platform from the Flow Navigator window or File > Export > Export Platform...

Select Hardware for Platform Type (the Kria doesn't currently have emulation support) and be sure to check the option to include the bitstream in Platform State. Give the platform the desired name, vendor/version info, description, and select the desired output directory for the exported platform.

At this point, this Vivado project is the perfect base for adding custom hardware to the design and then importing into Vitis and/or PetaLinux. Next week, I'll be posting how to pull this exported platform into PetaLinux 2022.1 and add hardware acceleration support to the kernel/root filesystem.