FPGAs are a great tool to democratize access to hardware design. As a single person I can basically design my own chip. Of course not a processor core competing with a Intel processor or an Arm application class core, but something comparable with a Cortex-M micro controller core.
For doing so RISC-V is a very good starting point, it is an open Instruction Set Architecture (ISA) developed originally by the EECS Department at the University of California, Berkeley and now maintained by the RISC-V foundation.
There are numerous implementations of the RISC-V specification, commercial and open source, in different hardware description languages and implemented as real silicon chips (e.g. SiFive FE310) but also on FPGAs.
This project uses my own implementation of a RISC-V core in VHDL (see link).
Of course a processor does not make up a full system, so this project also contains a lot of other stuff, like caches, memory interface, I/O, network, etc.
Not everything in it is open source, e.g. the DRAM controller or the ethernet core are proprietary Xilinx IP cores, especially for accessing the DRAM there is not much choice. But all cores are part of the no-cost Vivado WebPack Edition.
The SoC is realized as IP Integrator Block Design in Vivado, with all Bonfire VHDL Code as RTL modules. For easy integration into a Block design the CPU core with three AXI4 ports is provided
A processor is not useful without software, one of the things that can be run on the board is eLua (http://www.eluaproject.net). Initially eLua was thought as a "real world example" to test the processor and the system, in the meantime has a bit developed as a passion on its own for me.
It has also be proven as very useful when bringing up new peripherals in the SoC design: With eLua it is easy to read/write I/O registers and write test programs for the peripheral RTL directly on the board. For example linkstat.lua reads the Ethernet Phy I/O registers to monitor and report the Ethernet Link status. Initially I wrote a small Ethernet loopback test program in Lua to understand the Xilinx Ethernet Lite core before writing the "real" Ethernet driver in C.
If you want to rebuilt the design from scratch follow these instructions.
The instructions may be a bit "sparse" at the moment, so in case you run in trouble, please create an GitHub issue.