Video Streaming 10G video over SFP+ using the SMT-135

Introduction

This project is based on the application demo AN 062: Example Design: Video Streaming Over 10 Gigabit Ethernet provided by Efinix. The example design has been modified to run on the SMT135-C and uses the VC MIPI IMX900 image sensor from Vision Components.

Unlike traditional FPGA design the Efinix FPGA tools utilise an abstraction layer called the Peripheral layer which sits between the core RTL logic and the physical pins of the FPGA. This allows a design to be ported between different FPGA packages and I/O configurations while leaving the core RTL unmodified.

This post will go through the steps or porting a design to a different Efinix part and also updated the design to the latest Efinty IDE version.

Porting the design

To begin the porting process the original AN 062 example design is opened in Efinix Efinty IDE v2026.1. The project was created using using v2024.2 so the IPs used in the design need to be upgraded, select 'Yes' to upgrade them.

Once the project IP has been upgraded the part need to be modified, this is done by selecting from the IDE menu bar, File > Edit Project. The project editor will open, the part currently being use is the Titanium Ti375N1156 part. Select the new device Ti135N676 which is the part used in the SMT135-C, the timing model can be left at 'C4'.

Once a new device has been selected the project will need to be rerun.

After the project has been rerun the Migration Design wizard is launched, select the option to 'Update Existing Design' the process begins by selecting 'Next'.

The device migration wizard will detect all issues related to the device migration, these relate to the I/O of the original design being targeted to a new device. These can be corrected by reassigning the signals from the core RTL to suitable peripheral locations.

By selecting 'Finish' the Efinix Interface Designer opens allowing configuration of the peripheral layer. The Design Issues are listed in the table and can be corrected by re-configuring the I/O interface for the signals from the core RTL.

There are 20 issues presented when migrating this design, we will address each one individually.

The first 3 errors relate to the GPIOs and are associated with the TX enable for the SFP+ modules, there are 4 SFP+ modules configured for the original demo and only 1 SFP+ avaiable on the SMT135-C. We can remove these 3 unused GPIO signals for SFP_TXDISABLE. Once removed there is fourth signal connected to the SFP_TXDISABLE[2] which is routed to a pin on the SMT135-C. This can also be removed as the SMT135-C contains a pullup which when left unconnected will always transmit.

From the top menu select Design > Generate Interface Output Files, this will update the issue list removing the issues we just corrected.

There are four signals which can be used as an additional JTAG connection for debugging the riscv on a separate JTAG link, this is known as the Soft Debug Tap. This requires routing four signals from an external JTAG debugger through the FPGA fabric through to the core. The Soft Debug Tap will not be used for debugging as the co-debug option also allows simultaneous riscv and logic debugging. These 4 signals can be deleted as show below.

When migrating to a different device the voltage for the I/O banks could be set to different standards. The SMT135-C voltage for the I/O rails are different to the original design and must be reconfigured. This is accomplished by selecting the 'I/O Banks' tab in the Design Explorer. The I/O Banks should be configured to the values listed below.

bank name=2A  iostd=1.8 V
bank name=2B  iostd=1.8 V
bank name=2C  iostd=1.8 V
bank name=4A  iostd=1.8 V
bank name=4B  iostd=1.8 V
bank name=BL0 iostd=3.3 V
bank name=BL1 iostd=3.3 V
bank name=BL2 iostd=1.8 V
bank name=BL3 iostd=3.3 V
bank name=BR0 iostd=3.3 V
bank name=BR1 iostd=3.3 V
bank name=TL2 iostd=3.3 V
bank name=TL3 iostd=1.8 V
bank name=TR1 iostd=1.8 V
bank name=TR2 iostd=1.8 V
bank name=TR3 iostd=3.3 V
bank name=TR5 iostd=1.8 V

The cam_en, cam_scl and cam_sda signals are required for the new design, but are assigned to incompatible pins. These can be reassigned be selecting from the top menu Design > Show/Hide GPIO Resource Assigner.

From the GPIO Resource Assigner the package pins can be reconfigured. The GPIO pins can be configured as below which corresponds to the correct signals for the SMT135-C.

GPIO signals are relatively straightforward to correct for new device, there are several more signals which can reassigned using the same method. The GPIO signals listed below should be configured to match the settings below.

There are two PLLs used for the design, these will both need re-configuring to accommodate the clocks available on the SMT135-C. The PLL pll_inst1 connects to an external clock through the Peripheral Layer which will require modification to the clock source.

The PLL pll_inst1 requires that the PLL resource be changed to PLL_TR0 using the 'Block Editor' tab, this is required to allow the new clock input pin to be assigned to this resource. The external clock should also be changed to select External Clock 0. As can be seen in the image below.

Select the 'Automated Clock Calculation' in button in 'Block Editor' to open the clock calculator wizard. The original design used a clock input of 25MHz, the SMT135-C clock input is 100MHz so this input need modified as can be seen below.

The PLL pll_inst2 also uses an external clock input, however the pin allocated in the demo design is the same as the SMT135-C so modification of the clock input is not needed. Selecting the Automated Clock Calculation button for the pll_inst2 will open the PLL Clock Calculator, Clock 3 Frequency should be changed to 800MHz as shown below.

The MIPI DPHY are hardwired to specific pins on the FPGA, so individual pin addressing is not necessary. As two MIPI resources are available the user has the option of selecting MIPI_RX_0 or MIPI_RX_1. Both the original demo and the SMT135-C both use MIPI_RX_0 so this can be left unchanged. The Lane Mapping for the SMT135-C is different to the original demo and requires modifying to the settings listed below.

The DDR for the SMT135-C is similar to the DRR used in the original demo, however there are some modifications required. In the 'Block Editor' for the DRR the memory density should be changed to 8G.

The DRR also uses a different pin configuration for the DDR interface pin, this can be modified my using the Pin Swizzling tab in the 'Block Editor'. The pin swizzling should be adjusted as outlined in the following images.

The Ethernet XGMII uses a different Quad Lane on the SMT135-C, this can be switched by selecting Q0_LN0 in XGMII Resource within the Block Editor tab.

Once these modifications have been completed the design can be rebuilt.

Building the design

To run the design on the SMT135-C the prebuilt software needs to loaded on the Sapphire core, when the FPGA is configured it will automatically run the software. This is done by selecting the IP : sapphire_gen core from the project tree and using the right mouse button select 'Configure'.

The IP Configuration box will use the prebuild app.hex file which will be written to the On-Chip RAM. Select Browse in the User Application Path and select the file located at

SMT135-C/video_streaming_10G_imx900/fpga/embedded_sw/sapphire_gen/software/standalone/app/build/app.hex

Generate the core once the file app.hex has been selected.

Select the 'Nut and Bolt' icon on the left to build the project, this will create the bit and hex files used to program the SMT135-C.

Programming the SMT135-C

Once the build is complete the FPGA can be programmed by selecting the programmer from the menu, Tools > Open Programmer. The hex file can be selected from the project outflow directory. The hex file contains the FPGA and the code to run on the Sapphire core. The Programming Mode should be SPI Active using JTAG Bridge.

To view the video output the supplied Python script must be from the PC with the 10G ethernet card installed. Run the python program from the folder.

SMT135-C/video_streaming_10G_SFP_imx900/scripts/showVideo.py

There are a list of python requirements that need to be installed located in the file requirements.txt

The live video stream will start playing on the python video viewer.