Hardware wrapper for Xilinx Varium C1100

**Work in Progress**

Introduction

This project is for creating your own designs on the Xilinx Varium C1100.

Xilinx supplies an XDC file and tutorials recommend renaming the connections in that file to what you have in your designs.

Exposing the pinout of the C1100 board in the XDC file to Vivado Block Design is user friendlier.

For doing so, this project supplies IP blocks that serve as hardware wrappers.

Prerequisites

A working Vivado installation, preferably on Linux.

If you got into trouble installing Vivado, please have a look at my blog: https://www.hackster.io/stonux/epu-ethereum-processing-unit-325c52

Download the IPs from https://github.com/stonux/C1100hww/blob/main/C1100hww.tar.bz2

Extract the IPs to your workspace

cd ~/workspace
tar xfvj ~/Downloads/C1100hww.tar.bz2

Starting a new project

We follow UG1526 on page 9:

The TCL console is the "bottom line" of Vivado:

Do not click on "Create Project", but enter the following command in the "Type a Tcl command here" line:

create_project C1100_hww_blinky ~/workspace/ -part XCU55N-FSVH2892-2L-E

where

• "C1100_hww_blinky" is your project name
• "~/workspace" is your Vivado workspace directory (where the project is stored)
• and "XCU55N-FSVH2892-2L-E" is the Vivado part number of the Varium C1100

In Vivado's IP Catalog, right click on the right pane and select "Add Repository...".

Select the directory ~/workspace/C1100hww

Now, click on "Create block design".

Add the following IPs:

• C1100_SysClk2
• Utility Buffer
• Clocking Wizard
• Binary Counter
• Constant
• Slice (we need 2 of them)
• WTF! the LEDs are gone :-(

check back later. Sorry.

Connect the IPs the following way (on the right hand side, the LEDs are missing):

Double click the clocking wizard.

Change the requested output frequency to 10 MHz. At the bottom, uncheck "reset" and "locked".

Double click the binary counter.

Change the output width to 24.

Double click the constant, set const width to 2 and const val to 2. We should now have a logic 0 on dout[0] and a logic 1 on dout[1].

Next WTF: how to connect dout[1] resp. Q[20] to a specific LED?

Some code preview

The Verilog code is as simple as this:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////
// Company: <private>
// Engineer: Beat Steiner
// 
// Create Date: 02/19/2022 07:27:54 PM
// Design Name: Hardware wrapper for Varium C1100's LEDs
// Module Name: C1100_LEDs
// Project Name: Hardware wrapper for Varium C1100
// Target Devices: Varium C1100
// Tool Versions: 2021.2
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// License: Apache 2.0
//////////////////////////////////////////////////////////////////////////////

module C1100_LEDs(

    input wire sqfp28_0_activity_led,
    input wire sqfp28_0_link_stat_ledg,
    input wire sqfp28_0_link_stat_ledy,
    
    output wire QSFP28_0_ACTIVITY_LED,
    output wire QSFP28_0_LINK_STAT_LEDG,
    output wire QSFP28_0_LINK_STAT_LEDY,
    
    
    input wire sqfp28_1_activity_led,
    input wire sqfp28_1_link_stat_ledg,
    input wire sqfp28_1_link_stat_ledy,
    
    output wire QSFP28_1_ACTIVITY_LED,
    output wire QSFP28_1_LINK_STAT_LEDG,
    output wire QSFP28_1_LINK_STAT_LEDY
    
    );
    
    assign QSFP28_0_ACTIVITY_LED   = sqfp28_0_activity_led; 
    assign QSFP28_0_LINK_STAT_LEDG = sqfp28_0_link_stat_ledg;
    assign QSFP28_0_LINK_STAT_LEDY = sqfp28_0_link_stat_ledy;
    
    assign QSFP28_1_ACTIVITY_LED   = sqfp28_1_activity_led; 
    assign QSFP28_1_LINK_STAT_LEDG = sqfp28_1_link_stat_ledg;
    assign QSFP28_1_LINK_STAT_LEDY = sqfp28_1_link_stat_ledy;
    
    
endmodule