Rajeev PatwariNathalie Chan King Choy
Published © Apache-2.0

Ultra96 FPGA-Accelerated Parallel N-Particle Gravity Sim

Demonstrating the scientific computational power of the small ZU3EG SoC by using 8 parallel floating point accelerators running at 200 MHz.

IntermediateFull instructions provided4 hours1,044

Things used in this project

Hardware components

Ultra96
Avnet Ultra96
V1
×1
Avnet AES-ACC-U96-PWR
×1
USB Cable Assembly, USB Type A Plug to Micro USB Type B Plug
USB Cable Assembly, USB Type A Plug to Micro USB Type B Plug
×1
Mini displayport cable
×1
MircroSD card
Must be 8 GB or larger
×1
DisplayPort monitor
×1
USB Mouse
Optional
×1
USB keyboard
Optional
×1

Software apps and online services

Vivado Design Suite
Xilinx Vivado Design Suite
Avnet Ultra96 Pynq image v2.4

Story

Read more

Schematics

Pipeline diagram

Illustrates how the pipeline is organized. This is not really a schematic, but the project checklist wouldn't turn complete until something got uploaded for schematic, even though it doesn't apply to this project...

Code

nbody_x86.py Python implementation of N-body particle simulation

Python
Run this Python implementation of the particle simulation to see how slow it is compared to the FPGA-accelerated version
##########################################################################
#    Copyright 2019 Xilinx
# 
#    Licensed under the Apache License, Version 2.0 (the "License");
#    you may not use this file except in compliance with the License.
#    You may obtain a copy of the License at
# 
#      http://www.apache.org/licenses/LICENSE-2.0
# 
#    Unless required by applicable law or agreed to in writing, software
#    distributed under the License is distributed on an "AS IS" BASIS,
#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#    See the License for the specific language governing permissions and
#    limitations under the License.
# 
##########################################################################
#
# 4/4/2019 - Rajeev Patwari
#
# N-Body simulations
# Software to simulate N-body interactions based on Newtonian Gravity 
# calculations. The system is confined to point mass bodies with some 
# limitations
# This simulation is inspiration to design FPGA accelerator
# Testcase#1 shows why FPGA parallel acceleration is required!
# 
# References:
#   1. http://cc.doc.ic.ac.uk/projects/prj_axel/nbody.html
#   
# SW installations: Anaconda with Python 3.7 from here
#    https://www.anaconda.com/distribution/
#
##########################################################################

import numpy as np
import matplotlib.pyplot as plt
import matplotlib.animation as animation
import mpl_toolkits.mplot3d.axes3d as p3
import random
import math

# ----------- configure before run - begin
# select a test case between 1 and 10
# uncomment one of the following
#testcase = 1  # n=500; very slow on pc - this is why we need accelerator!
testcase = 2  # n=2
#testcase = 3  # n=12
#testcase = 4  # n=3
#testcase = 5  # n=500; very slow on PC
#testcase = 6  # n=500; very slow on PC
#testcase = 7  # n=500; very slow on PC
# ----------- configure before run - end


# Fixing random state for reproducibility
random.seed(19680801)

# initialize particle positions, mass and initial velocity
graphlim = 4000
numparticles = 500
timestep = np.float(100)

if testcase==1:
    x      = list(np.random.uniform(-3000,3000,numparticles))
    y      = list(np.random.uniform(-3000,3000,numparticles))
    z      = list(np.random.uniform(-3000,3000,numparticles))
    mass   = list(np.random.uniform(100,110,numparticles))
    vx     = list(np.random.uniform(0,0,numparticles ))
    vy     = list(np.random.uniform(0,0,numparticles ))
    vz     = list(np.random.uniform(0,0,numparticles ))
    mass[0] = 100
    sf = 4000.0

elif testcase==2:
    x      = [300, -300]
    y      = [0,0]
    z      = [0,0]
    mass   = [295, 300]
    vx     = [-0.1,0]
    vy     = [0.1,0]
    vz     = [0,0]
    sf = 600.0
    numparticles = 2

elif testcase==3:
    numparticles = 12
    x      = [100, 100, -100,-100, 100, 100, -100,-100, 100, 100, -100,-100]
    y      = [100, -100, 100, -100,100, -100, 100, -100, 100, -100, 100, -100]
    z      = [0,  0, 0, 0, 100,  100, 100, 100, -100,-100, -100, -100]
    mass   = [0.5 for i in range(0,numparticles,1)]
    vx     = [0.0 for i in range(0,numparticles,1)]
    vy     = [0.0 for i in range(0,numparticles,1)]
    vz     = [0.0 for i in range(0,numparticles,1)]
    sf = 200.0
    
elif testcase==4: # 2 planets trying to orbit a star
    numparticles = 3
    x      = [0, 0, 10]
    y      = [0, 25, 10]
    z      = [0,  0, 0 ]
    mass   = [10, 10, 5]
    vx     = [0.0, 0.0, 0.0]
    vy     = [0.0, 0.0, 0.0 ]
    vz     = [0.0, 0.0, 0.0]
    sf = 2
    graphlim = 800
    timestep = np.float(1)

elif testcase==5:
    lim = 3000.0/2
    x      = list(lim*np.random.random_sample((numparticles,)))
    y      = list(lim*np.random.random_sample((numparticles,)))
    z      = list(lim*np.random.random_sample((numparticles,)))
    mass   = list(3000*np.random.random_sample((numparticles,)))
    vx     = list(np.random.uniform(-1,1,numparticles ))
    vy     = list(np.random.uniform(-1,1,numparticles ))
    vz     = list(np.random.uniform(-1,1,numparticles ))
    mass[0] = 100
    sf = 4000.0
    graphlim = 8000
	
elif testcase==6:
    radius, h_max, v_max = 1000, 1280, 720
    theta = np.linspace(0, 2*np.pi, numparticles)
    a, b = 1 * np.cos(theta), 1 * np.sin(theta)
    r = np.random.rand((numparticles))
    x, y = radius*r * np.cos(theta), radius*r * np.sin(theta)
    x = [int(i+640) for i in x]
    y = [int(i+360) for i in y]
    mass = [random.randint(10, 110) for i in range(0, numparticles)]  
    z = [0 for i in range(0, numparticles)] 
    #x[0], y[0], mass[0] = 640, 360, 10000
    vx = [0 for i in range(0, numparticles)] 
    vy = [0 for i in range(0, numparticles)] 
    vz = [0 for i in range(0, numparticles)] 
    sf = 300.0
    timestep = np.float(5)
    graphlim = 1500
    
else:
    print ("Chose between 1 to 6 and re-run")	
	
	
# Create new Figure with black background
fig = plt.figure()
ax = p3.Axes3D(fig)

# Add a subplot with no frame, set limits
ax.set_xlim3d(-graphlim, graphlim)
ax.set_ylim3d(-graphlim, graphlim)
ax.set_zlim3d(-graphlim, graphlim)
ax.set_xlabel('X Label')
ax.set_ylabel('Y Label')
ax.set_zlabel('Z Label')
print(len(x), len(y), len(z), len(vx), len(vy), len(vz), len(mass))

def update(*args):
    """ can be parameerized if needed """
	
    global x,y,vx,vy,mass,numparticles, sf
    accx = [0.0 for i in range(0, numparticles)]
    accy = [0.0 for i in range(0, numparticles)]
    accz = [0.0 for i in range(0, numparticles)]
    for i in range(0, numparticles, 1):
        for j in range(0, numparticles, 1):
            if (j!=i):
                rx = x[j] - x[i]
                ry = y[j] - y[i]
                rz = z[j] - z[i]
                dd = np.power(rx,2) + np.power(ry,2) + np.power(rz,2) + sf*sf
                #print(np.power(dd,3))
                d = 1/np.sqrt(np.power(dd,3))
                s = mass[j]*d
                accx[i] += rx*s 
                accy[i] += ry*s 
                accz[i] += rz*s 
        
        #print(accx[0], x[0]) 
        x[i] += vx[i]*timestep
        y[i] += vy[i]*timestep
        z[i] += vz[i]*timestep
        vx[i] += accx[i]*timestep
        vy[i] += accy[i]*timestep
        vz[i] += accz[i]*timestep
    ax.clear()  
    ax.scatter(x,y,z,'.')
    ax.set_xlim3d(-graphlim, graphlim)
    ax.set_ylim3d(-graphlim, graphlim)
    ax.set_zlim3d(-graphlim, graphlim)
    ax.set_xlabel('X Label')
    ax.set_ylabel('Y Label')
    ax.set_zlabel('Z Label')
    return 
	
# Construct the animation, using the update function as the animation director.
anim = animation.FuncAnimation(fig, update, interval=10)
plt.show()
anim.save('nbody_pc_sim1.html')

#with np.errstate(over='ignore'):
                

nbodypynq.bit Pre-built bitstream for Pynq overlay

Plain text
Provided for those who don't want to build the Vivado project. See Story instructions for location to copy the bitstream to. It's labeled as "Plain text" since no option is available for "FPGA bitstream".
No preview (download only).

nbodypynq.tcl Pre-built TCL script for Pynq overlay

Tcl
Provided for those who don't want to build the Vivado project. See Story instructions for location to copy the overlay TCL to.
##########################################################################
# 
#    Copyright 2019 Xilinx 
#
#    Licensed under the Apache License, Version 2.0 (the "License");
#    you may not use this file except in compliance with the License.
#    You may obtain a copy of the License at
# 
#      http://www.apache.org/licenses/LICENSE-2.0
# 
#    Unless required by applicable law or agreed to in writing, software
#    distributed under the License is distributed on an "AS IS" BASIS,
#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#    See the License for the specific language governing permissions and
#    limitations under the License.
# 
##########################################################################


################################################################
# This is a generated script based on design: design_1
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./nbody/nbodyproj.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project nbodyproj nbody -part xczu3eg-sbva484-1-i
}


# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_1

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
   return $nRet
}

set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
   set list_check_ips "\ 
xilinx.com:ip:axi_apb_bridge:3.0\
xilinx.com:ip:axi_uart16550:2.0\
xilinx.com:ip:clk_wiz:6.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:zynq_ultra_ps_e:3.2\
"

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 3
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder
  variable design_name

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set APB_M [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:apb_rtl:1.0 APB_M ]
  set APB_M2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:apb_rtl:1.0 APB_M2 ]
  set APB_M3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:apb_rtl:1.0 APB_M3 ]
  set gpio_sensors [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sensors ]
  set uart1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart1 ]

  # Create ports
  set bt_ctsn [ create_bd_port -dir I bt_ctsn ]
  set bt_rtsn [ create_bd_port -dir O bt_rtsn ]
  set peripheral_reset [ create_bd_port -dir O -from 0 -to 0 -type rst peripheral_reset ]
  set pl_clk1 [ create_bd_port -dir O -type clk pl_clk1 ]
  set pl_clk2_300MHz [ create_bd_port -dir O -type clk pl_clk2_300MHz ]
  set pl_clk3_374MHz [ create_bd_port -dir O -type clk pl_clk3_374MHz ]
  set pll_locked [ create_bd_port -dir O pll_locked ]
  set uart0_ctsn [ create_bd_port -dir I -type data uart0_ctsn ]
  set uart0_rtsn [ create_bd_port -dir O -type data uart0_rtsn ]
  set uart0_rxd [ create_bd_port -dir I uart0_rxd ]
  set uart0_txd [ create_bd_port -dir O uart0_txd ]

  # Create instance: axi_apb_bridge_0, and set properties
  set axi_apb_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_apb_bridge:3.0 axi_apb_bridge_0 ]
  set_property -dict [ list \
   CONFIG.C_APB_NUM_SLAVES {3} \
 ] $axi_apb_bridge_0

  # Create instance: axi_uart16550_0, and set properties
  set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ]
  set_property -dict [ list \
   CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999901} \
 ] $axi_uart16550_0

  # Create instance: clk_wiz_0, and set properties
  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
  set_property -dict [ list \
   CONFIG.CLKIN1_JITTER_PS {400.0} \
   CONFIG.CLKOUT1_DRIVES {BUFGCE} \
   CONFIG.CLKOUT1_JITTER {175.029} \
   CONFIG.CLKOUT1_PHASE_ERROR {222.305} \
   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
   CONFIG.CLKOUT2_DRIVES {BUFGCE} \
   CONFIG.CLKOUT3_DRIVES {BUFGCE} \
   CONFIG.CLKOUT4_DRIVES {BUFGCE} \
   CONFIG.CLKOUT5_DRIVES {BUFGCE} \
   CONFIG.CLKOUT6_DRIVES {BUFGCE} \
   CONFIG.CLKOUT7_DRIVES {BUFGCE} \
   CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
   CONFIG.MMCM_CLKFBOUT_MULT_F {48.000} \
   CONFIG.MMCM_CLKIN1_PERIOD {40.000} \
   CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
   CONFIG.MMCM_CLKOUT0_DIVIDE_F {6.000} \
   CONFIG.MMCM_DIVCLK_DIVIDE {1} \
   CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
   CONFIG.USE_PHASE_ALIGNMENT {true} \
   CONFIG.USE_SAFE_CLOCK_STARTUP {true} \
 ] $clk_wiz_0

  # Create instance: proc_sys_reset_0, and set properties
  set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]

  # Create instance: proc_sys_reset_1, and set properties
  set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]

  # Create instance: ps8_0_axi_periph, and set properties
  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
  set_property -dict [ list \
   CONFIG.NUM_MI {2} \
 ] $ps8_0_axi_periph

  # Create instance: zynq_ultra_ps_e_0, and set properties
  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 zynq_ultra_ps_e_0 ]
  set_property -dict [ list \
   CONFIG.CAN0_BOARD_INTERFACE {custom} \
   CONFIG.CAN1_BOARD_INTERFACE {custom} \
   CONFIG.CSU_BOARD_INTERFACE {custom} \
   CONFIG.DP_BOARD_INTERFACE {custom} \
   CONFIG.GEM0_BOARD_INTERFACE {custom} \
   CONFIG.GEM1_BOARD_INTERFACE {custom} \
   CONFIG.GEM2_BOARD_INTERFACE {custom} \
   CONFIG.GEM3_BOARD_INTERFACE {custom} \
   CONFIG.GPIO_BOARD_INTERFACE {custom} \
   CONFIG.IIC0_BOARD_INTERFACE {custom} \
   CONFIG.IIC1_BOARD_INTERFACE {custom} \
   CONFIG.NAND_BOARD_INTERFACE {custom} \
   CONFIG.PCIE_BOARD_INTERFACE {custom} \
   CONFIG.PJTAG_BOARD_INTERFACE {custom} \
   CONFIG.PMU_BOARD_INTERFACE {custom} \
   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
   CONFIG.PSU_IMPORT_BOARD_PRESET {} \
   CONFIG.PSU_MIO_0_DIRECTION {inout} \
   CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_0_SLEW {slow} \
   CONFIG.PSU_MIO_10_DIRECTION {inout} \
   CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_10_SLEW {slow} \
   CONFIG.PSU_MIO_11_DIRECTION {inout} \
   CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_11_SLEW {slow} \
   CONFIG.PSU_MIO_12_DIRECTION {inout} \
   CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_12_SLEW {slow} \
   CONFIG.PSU_MIO_13_DIRECTION {inout} \
   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_13_SLEW {slow} \
   CONFIG.PSU_MIO_14_DIRECTION {inout} \
   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_14_SLEW {slow} \
   CONFIG.PSU_MIO_15_DIRECTION {inout} \
   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_15_SLEW {slow} \
   CONFIG.PSU_MIO_16_DIRECTION {inout} \
   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_16_SLEW {slow} \
   CONFIG.PSU_MIO_17_DIRECTION {inout} \
   CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_17_SLEW {slow} \
   CONFIG.PSU_MIO_18_DIRECTION {inout} \
   CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_18_SLEW {slow} \
   CONFIG.PSU_MIO_19_DIRECTION {inout} \
   CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_19_SLEW {slow} \
   CONFIG.PSU_MIO_1_DIRECTION {inout} \
   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_1_SLEW {slow} \
   CONFIG.PSU_MIO_20_DIRECTION {inout} \
   CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_20_SLEW {slow} \
   CONFIG.PSU_MIO_21_DIRECTION {inout} \
   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_21_SLEW {slow} \
   CONFIG.PSU_MIO_22_DIRECTION {out} \
   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_22_SLEW {slow} \
   CONFIG.PSU_MIO_23_DIRECTION {inout} \
   CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_23_SLEW {slow} \
   CONFIG.PSU_MIO_24_DIRECTION {in} \
   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_24_SLEW {slow} \
   CONFIG.PSU_MIO_25_DIRECTION {inout} \
   CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_25_SLEW {slow} \
   CONFIG.PSU_MIO_26_DIRECTION {inout} \
   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_26_SLEW {slow} \
   CONFIG.PSU_MIO_27_DIRECTION {out} \
   CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_27_SLEW {slow} \
   CONFIG.PSU_MIO_28_DIRECTION {in} \
   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_28_SLEW {slow} \
   CONFIG.PSU_MIO_29_DIRECTION {out} \
   CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_29_SLEW {slow} \
   CONFIG.PSU_MIO_2_DIRECTION {in} \
   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_2_SLEW {slow} \
   CONFIG.PSU_MIO_30_DIRECTION {in} \
   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_30_SLEW {slow} \
   CONFIG.PSU_MIO_31_DIRECTION {inout} \
   CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_31_SLEW {slow} \
   CONFIG.PSU_MIO_32_DIRECTION {out} \
   CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_32_SLEW {slow} \
   CONFIG.PSU_MIO_33_DIRECTION {out} \
   CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_33_SLEW {slow} \
   CONFIG.PSU_MIO_34_DIRECTION {inout} \
   CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_34_SLEW {slow} \
   CONFIG.PSU_MIO_35_DIRECTION {inout} \
   CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_35_SLEW {slow} \
   CONFIG.PSU_MIO_36_DIRECTION {inout} \
   CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_36_SLEW {slow} \
   CONFIG.PSU_MIO_37_DIRECTION {inout} \
   CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_37_SLEW {slow} \
   CONFIG.PSU_MIO_38_DIRECTION {inout} \
   CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_38_SLEW {slow} \
   CONFIG.PSU_MIO_39_DIRECTION {inout} \
   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_39_SLEW {slow} \
   CONFIG.PSU_MIO_3_DIRECTION {out} \
   CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_3_SLEW {slow} \
   CONFIG.PSU_MIO_40_DIRECTION {inout} \
   CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_40_SLEW {slow} \
   CONFIG.PSU_MIO_41_DIRECTION {inout} \
   CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_41_SLEW {slow} \
   CONFIG.PSU_MIO_42_DIRECTION {inout} \
   CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_42_SLEW {slow} \
   CONFIG.PSU_MIO_43_DIRECTION {inout} \
   CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_43_SLEW {slow} \
   CONFIG.PSU_MIO_44_DIRECTION {inout} \
   CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_44_SLEW {slow} \
   CONFIG.PSU_MIO_45_DIRECTION {inout} \
   CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_45_SLEW {slow} \
   CONFIG.PSU_MIO_46_DIRECTION {inout} \
   CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_46_SLEW {slow} \
   CONFIG.PSU_MIO_47_DIRECTION {inout} \
   CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_47_SLEW {slow} \
   CONFIG.PSU_MIO_48_DIRECTION {inout} \
   CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_48_SLEW {slow} \
   CONFIG.PSU_MIO_49_DIRECTION {inout} \
   CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_49_SLEW {slow} \
   CONFIG.PSU_MIO_4_DIRECTION {inout} \
   CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_4_SLEW {slow} \
   CONFIG.PSU_MIO_50_DIRECTION {inout} \
   CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_50_SLEW {slow} \
   CONFIG.PSU_MIO_51_DIRECTION {out} \
   CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_51_SLEW {slow} \
   CONFIG.PSU_MIO_52_DIRECTION {in} \
   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_52_SLEW {slow} \
   CONFIG.PSU_MIO_53_DIRECTION {in} \
   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_53_SLEW {slow} \
   CONFIG.PSU_MIO_54_DIRECTION {inout} \
   CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_54_SLEW {slow} \
   CONFIG.PSU_MIO_55_DIRECTION {in} \
   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_55_SLEW {slow} \
   CONFIG.PSU_MIO_56_DIRECTION {inout} \
   CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_56_SLEW {slow} \
   CONFIG.PSU_MIO_57_DIRECTION {inout} \
   CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_57_SLEW {slow} \
   CONFIG.PSU_MIO_58_DIRECTION {out} \
   CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_58_SLEW {slow} \
   CONFIG.PSU_MIO_59_DIRECTION {inout} \
   CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_59_SLEW {slow} \
   CONFIG.PSU_MIO_5_DIRECTION {inout} \
   CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_5_SLEW {slow} \
   CONFIG.PSU_MIO_60_DIRECTION {inout} \
   CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_60_SLEW {slow} \
   CONFIG.PSU_MIO_61_DIRECTION {inout} \
   CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_61_SLEW {slow} \
   CONFIG.PSU_MIO_62_DIRECTION {inout} \
   CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_62_SLEW {slow} \
   CONFIG.PSU_MIO_63_DIRECTION {inout} \
   CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_63_SLEW {slow} \
   CONFIG.PSU_MIO_64_DIRECTION {in} \
   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_64_SLEW {slow} \
   CONFIG.PSU_MIO_65_DIRECTION {in} \
   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_65_SLEW {slow} \
   CONFIG.PSU_MIO_66_DIRECTION {inout} \
   CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_66_SLEW {slow} \
   CONFIG.PSU_MIO_67_DIRECTION {in} \
   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_67_SLEW {slow} \
   CONFIG.PSU_MIO_68_DIRECTION {inout} \
   CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_68_SLEW {slow} \
   CONFIG.PSU_MIO_69_DIRECTION {inout} \
   CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_69_SLEW {slow} \
   CONFIG.PSU_MIO_6_DIRECTION {inout} \
   CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_6_SLEW {slow} \
   CONFIG.PSU_MIO_70_DIRECTION {out} \
   CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_70_SLEW {slow} \
   CONFIG.PSU_MIO_71_DIRECTION {inout} \
   CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_71_SLEW {slow} \
   CONFIG.PSU_MIO_72_DIRECTION {inout} \
   CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_72_SLEW {slow} \
   CONFIG.PSU_MIO_73_DIRECTION {inout} \
   CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_73_SLEW {slow} \
   CONFIG.PSU_MIO_74_DIRECTION {inout} \
   CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_74_SLEW {slow} \
   CONFIG.PSU_MIO_75_DIRECTION {inout} \
   CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_75_SLEW {slow} \
   CONFIG.PSU_MIO_76_DIRECTION {inout} \
   CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_76_SLEW {slow} \
   CONFIG.PSU_MIO_77_DIRECTION {inout} \
   CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_77_SLEW {slow} \
   CONFIG.PSU_MIO_7_DIRECTION {inout} \
   CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_7_SLEW {slow} \
   CONFIG.PSU_MIO_8_DIRECTION {inout} \
   CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_8_SLEW {slow} \
   CONFIG.PSU_MIO_9_DIRECTION {inout} \
   CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_9_SLEW {slow} \
   CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
   CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
   CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
   CONFIG.PSU_SMC_CYCLE_T0 {NA} \
   CONFIG.PSU_SMC_CYCLE_T1 {NA} \
   CONFIG.PSU_SMC_CYCLE_T2 {NA} \
   CONFIG.PSU_SMC_CYCLE_T3 {NA} \
   CONFIG.PSU_SMC_CYCLE_T4 {NA} \
   CONFIG.PSU_SMC_CYCLE_T5 {NA} \
   CONFIG.PSU_SMC_CYCLE_T6 {NA} \
   CONFIG.PSU_VALUE_SILVERSION {3} \
   CONFIG.PSU__ACPU0__POWER__ON {1} \
   CONFIG.PSU__ACPU1__POWER__ON {1} \
   CONFIG.PSU__ACPU2__POWER__ON {1} \
   CONFIG.PSU__ACPU3__POWER__ON {1} \
   CONFIG.PSU__ACTUAL__IP {1} \
   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.332825} \
   CONFIG.PSU__AFI0_COHERENCY {0} \
   CONFIG.PSU__AFI1_COHERENCY {0} \
   CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
   CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
   CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
   CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.998901} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
   CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
   CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
   CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999756} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999756} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666412} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999451} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576017} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214418} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029297} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999451} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.999512} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
   CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999901} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.332825} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.333} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.999512} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724087} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999512} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999756} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.998535} \
   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999901} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.999756} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999901} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.999512} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499817} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999901} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999695} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999634} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.499817} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.499817} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.499817} \
...

This file has been truncated, please download it to see its full contents.

apb3_bram_cntrl.v

Verilog
Copy to <workspace>/src
Custom APB3 based memory controller to interface TX and RX RAMs that store int16 values
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//    Copyright 2019 Xilinx
// 
//    Licensed under the Apache License, Version 2.0 (the "License");
//    you may not use this file except in compliance with the License.
//    You may obtain a copy of the License at
// 
//      http://www.apache.org/licenses/LICENSE-2.0
// 
//    Unless required by applicable law or agreed to in writing, software
//    distributed under the License is distributed on an "AS IS" BASIS,
//    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//    See the License for the specific language governing permissions and
//    limitations under the License.
// 
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Rajeev Patwari
// 
// Create Date: 05/23/2018 07:05:44 PM
// Design Name: 
// Module Name: apb3_bram_cntrr
// Project Name: ZZSoC Proj 2 Nbody sim
// Target Devices: XCZU3EG 
// Tool Versions: 2018.3
// Description: 
//     Custom APB3 based memory controller to interface TX and RX RAMs that 
//     store int16 values 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.02 - Edited filename, changed addr with to 15 bits and added comments
// Additional Comments:
//   1. All code was designed and developed by me.
//   2. This engine receives commands from APB3 bus (through AXI to APB bridge) 
//      and decides where the WRITES/READS should be diverted to.
//   3. In sort, this acts like a mini memory controller
//////////////////////////////////////////////////////////////////////////////////

`define RAM_DEPTH 512

module apb3_bram_cntrl(
                 clk,
                 rst_in,
                 APB_M_paddr, // rx
                 APB_M_penable,
                 APB_M_psel,
                 APB_M_pwdata,
                 APB_M_pwrite,
                 APB_M_pready,
                 APB_M_prdata,
                 APB_M_pslverr,
                 APB_M2_paddr, // tx
                 APB_M2_penable,
                 APB_M2_psel,
                 APB_M2_pwdata,
                 APB_M2_pwrite,
                 APB_M2_pready,
                 APB_M2_prdata,
                 APB_M2_pslverr,
                 
                 // rx ram - write to this ram through sw
                 // the following signals are generated from apb3 bram controller to write to rxram
                 addra_rxram0,  
                 dina_rxram0, 
                 wea_rxram0, 
                 ena_rxram0,
                 douta_rxram0, 
                 
                 addra_rxram1,  
                 dina_rxram1, 
                 wea_rxram1, 
                 ena_rxram1,
                 douta_rxram1, 
                                                   
                 // tx bram - read from this ram through sw
                 // the following signals are generated from apb3 bram controller to read from txram
                 addrb_txram0,  
                 enb_txram0,
                 doutb_txram0, 
  
                 addrb_txram1,  
                 enb_txram1,
                 doutb_txram1                     
);
  
  input clk;
  input rst_in;
  input wire [31:0]   APB_M_paddr;
  input wire          APB_M_penable;
  input wire [0:0]    APB_M_psel;
  input wire [31:0]   APB_M_pwdata;
  input wire          APB_M_pwrite;

  output wire [0:0]   APB_M_pready;
  output wire [31:0]  APB_M_prdata;
  output wire         APB_M_pslverr;
  
  input wire [31:0]   APB_M2_paddr;
  input wire          APB_M2_penable;
  input wire [0:0]    APB_M2_psel;
  input wire [31:0]   APB_M2_pwdata;
  input wire          APB_M2_pwrite;
  
  output wire [0:0]   APB_M2_pready;
  output wire [31:0]  APB_M2_prdata;
  output wire         APB_M2_pslverr;
  
  output wire [15:0]   addra_rxram0;
  output wire [31:0]  dina_rxram0;
  output wire         wea_rxram0;
  output wire         ena_rxram0;
  input wire  [31:0]  douta_rxram0;
   
  output wire [15:0]   addra_rxram1;
  output wire [31:0]  dina_rxram1;
  output wire         wea_rxram1;
  output wire         ena_rxram1;
  input wire  [31:0]  douta_rxram1;  
  
  output wire [15:0]   addrb_txram0;
  output wire         enb_txram0;
  input wire  [31:0]  doutb_txram0;  

  output wire [15:0]   addrb_txram1;
  output wire         enb_txram1;
  input wire  [31:0]  doutb_txram1;
    
  wire [15:0] rxaddr, txaddr;
  wire [15:0]  rxram_row_num, txram_row_num;
  wire        is_rxram1, is_txram1;
  wire        rxram_wr_en, txram_wr_en;
  
      // local reset synchronizer
  wire rst;
  reset_pipe rst_pipe_apb3_bram_cntrl (.clk(clk), .rst_in(rst_in), .rst_out(rst));
  //assign rst = rst_in;
  //---------    
      
  // APB_M_addr is 16b address
  // 0x0, 0x4, 0x8..
  // apb - m  - rxram0 - 0x0000 to 0x7FFF
  // apb - m  - rxram1 - 0x8000 to 0xFFFF
  // apb - m2 - txram  - 0x0000 to 0x7FFF
  // rxram and txram addresses are just row nums (APB_M_addr>>2)   
  
  // rx brams : control - rxram0 has x,y & rxram1 has z,mass 
  assign rxaddr         = APB_M_paddr[15:0]>>2;
  assign rxram_row_num  = {1'b0,rxaddr[14:0]};
  assign is_rxram1      = APB_M_paddr[15];
  assign APB_M_pready   = 1'b1;
  assign rxram_wr_en    = APB_M_penable &&  APB_M_psel && APB_M_pwrite;
  
  assign addra_rxram0 = rxram_row_num;
  assign dina_rxram0  = (rxram_wr_en && ~is_rxram1) ? APB_M_pwdata : 32'd0;
  assign wea_rxram0   = (rxram_wr_en && ~is_rxram1) ? 1'b1 : 1'd0;
  assign ena_rxram0   = (~is_rxram1) ? 1'b1 : 1'd0;
  
  assign addra_rxram1 = rxram_row_num;
  assign dina_rxram1  = (rxram_wr_en && is_rxram1) ? APB_M_pwdata : 32'd0;
  assign wea_rxram1   = (rxram_wr_en && is_rxram1) ? 1'b1 : 1'd0;
  assign ena_rxram1   = (is_rxram1) ? 1'b1 : 1'd0;
        
  assign APB_M_prdata = (is_rxram1) ? douta_rxram1 : douta_rxram0;
  assign APB_M_pslverr = 1'b0;  
    
  // tx brams : control -  
  assign txaddr         = APB_M2_paddr[15:0]>>2;
  assign txram_row_num  = {1'b0,txaddr[14:0]};
  assign is_txram1      = APB_M2_paddr[15];
  assign APB_M2_pready   = 1'b1;
    
  assign addrb_txram0    = txram_row_num;
  assign addrb_txram1    = txram_row_num;
  assign enb_txram0      = 1'b1;    
  assign enb_txram1      = 1'b1;    
  assign txram_wr_en    = 1'b0;
  
  assign APB_M2_pslverr = 1'b0;
  assign APB_M2_prdata = (is_txram1) ? doutb_txram1 : doutb_txram0;
        
endmodule

apb3_regbank.v

Verilog
Copy to <workspace>/src
Custom APB based control and status register space.
User can trigger accelerator and collect status signals from PL
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//    Copyright 2019 Xilinx
// 
//    Licensed under the Apache License, Version 2.0 (the "License");
//    you may not use this file except in compliance with the License.
//    You may obtain a copy of the License at
// 
//      http://www.apache.org/licenses/LICENSE-2.0
// 
//    Unless required by applicable law or agreed to in writing, software
//    distributed under the License is distributed on an "AS IS" BASIS,
//    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//    See the License for the specific language governing permissions and
//    limitations under the License.
// 
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Rajeev Patwari
// 
// Create Date: 04/18/2018 08:30:50 PM
// Design Name: 
// Module Name: apb3_regbank
// Project Name: ZZSoC Proj 2 Nbody sim
// Target Devices: XCZU3EG
// Tool Versions: 2018.3
// Description: 
//     Custome APB based control and status register space.
//     User can trigger accelerator and collect status signals from PL
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//   All code designed, developed by me.
//////////////////////////////////////////////////////////////////////////////////


module apb3_regbank(
                           clk,
                           rst_in,
                           APB_M_paddr,
                           APB_M_penable,
                           APB_M_psel,
                           APB_M_pwdata,
                           APB_M_pwrite,
                           APB_M_pready,
                           APB_M_prdata,
                           APB_M_pslverr,
                           reg0,
                           reg1,
                           reg2,
                           reg3,
                           outreg0,
                           outreg1,
                           outreg2,
                           outreg3,
                           outreg4,
                           outreg5,
                           outreg6,
                           outreg7    
                         );
    
    input clk;
    input rst_in;
    input wire [31:0]   APB_M_paddr;
    input wire          APB_M_penable;
    input wire [0:0]    APB_M_psel;
    input wire [31:0]   APB_M_pwdata;
    input wire          APB_M_pwrite;

    output wire [0:0]   APB_M_pready;
    output reg  [31:0]  APB_M_prdata;
    output wire         APB_M_pslverr;
    
    
    output reg [31:0] reg0;
    output reg [31:0] reg1;
    output reg [31:0] reg2;
    output reg [31:0] reg3;
    
    input wire [31:0] outreg0;
    input wire [31:0] outreg1;
    input wire [31:0] outreg2;
    input wire [31:0] outreg3;
    input wire [31:0] outreg4;
    input wire [31:0] outreg5;
    input wire [31:0] outreg6;
    input wire [31:0] outreg7;
    
    wire           rdb_wr_a;
    wire [15:0]    addr;
    
    // local reset synchronizer
    wire rst;
    reset_pipe rst_pipe0 (.clk(clk), .rst_in(rst_in), .rst_out(rst));
    //assign rst = rst_in;
    //---------    
    
    assign addr = APB_M_paddr[15:0];
    assign APB_M_pready = 1'b1;
    assign APB_M_pslverr = 1'b0;
    
    assign rdb_wr_a =    APB_M_penable &&  APB_M_psel && APB_M_pwrite;
    
    always@(posedge clk)
    begin
      if (rst) begin
          reg0 <= 32'd0;
          reg1 <= 32'd0;
          reg2 <= 32'd0;
          reg3 <= 32'd0;
      end
      else
      begin
          if (rdb_wr_a)
            begin
              case (addr)
                'h0: begin
                    reg0 <= APB_M_pwdata;
                end
                'h4: begin
                    reg1 <= APB_M_pwdata;
                end
                'h8: begin
                    reg2 <= APB_M_pwdata;
                end
                'hc: begin
                    reg3 <= APB_M_pwdata;
                end
                default: begin
                    reg0 <= reg0;
                    reg1 <= reg1;
                    reg2 <= reg2;
                    reg3 <= reg3;
                end
              endcase
          end
      end
    end
    
    always@(*)
    begin
      case (addr)
        'h0:  APB_M_prdata = reg0;
        'h4:  APB_M_prdata = reg1;
        'h8:  APB_M_prdata = reg2;
        'hc:  APB_M_prdata = reg3;
        'h80: APB_M_prdata = outreg0;
        'h84: APB_M_prdata = outreg1;
        'h88: APB_M_prdata = outreg2;
        'h8c: APB_M_prdata = outreg3;
        'h90: APB_M_prdata = outreg4;
        'h94: APB_M_prdata = outreg5;
        'h98: APB_M_prdata = outreg6;
        'h9c: APB_M_prdata = outreg7;
                                                                          
       default: begin
          APB_M_prdata = 32'd0;
        end
      endcase
        
    end                       
 
endmodule

compute_engine.v

Verilog
Copy to <workspace>/src
Main compute engine. This decides whether to instantiate single gravity engine or parallel engines
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//    Copyright 2019 Xilinx
// 
//    Licensed under the Apache License, Version 2.0 (the "License");
//    you may not use this file except in compliance with the License.
//    You may obtain a copy of the License at
// 
//      http://www.apache.org/licenses/LICENSE-2.0
// 
//    Unless required by applicable law or agreed to in writing, software
//    distributed under the License is distributed on an "AS IS" BASIS,
//    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//    See the License for the specific language governing permissions and
//    limitations under the License.
// 
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Rajeev Patwari
// 
// Create Date: 04/18/2018 08:11:36 PM
// Design Name: compute engine
// Module Name: compute_engine
// Project Name: ZZSoC Proj 2
// Target Devices: XCZu3EG
// Tool Versions: 2018.3
// Description: 
//     Main compute engine. This decides whether to instantiate single gravity engine or 
//     parallel engines
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//   All code designed and developed by me
//////////////////////////////////////////////////////////////////////////////////


module compute_engine(
        rst,
        APB_M_paddr,
        APB_M_penable,
        APB_M_prdata,
        APB_M_pready,
        APB_M_psel,
        APB_M_pslverr,
        APB_M_pwdata,
        APB_M_pwrite,
        APB_M2_paddr,
        APB_M2_penable,
        APB_M2_prdata,
        APB_M2_pready,
        APB_M2_psel,
        APB_M2_pslverr,
        APB_M2_pwdata,
        APB_M2_pwrite,
        APB_M3_paddr,
        APB_M3_penable,
        APB_M3_prdata,
        APB_M3_pready,
        APB_M3_psel,
        APB_M3_pslverr,
        APB_M3_pwdata,
        APB_M3_pwrite,
        pll_locked,
        pl_clk1,
        pl_clk2_300MHz,
        pl_clk3_374MHz
        );
      
      input  wire [31:0]  APB_M_paddr;
      input  wire         APB_M_penable;
      output wire [31:0]  APB_M_prdata;
      output wire [0:0]   APB_M_pready;
      input  wire [0:0]   APB_M_psel;
      output wire [0:0]   APB_M_pslverr;
      input  wire [31:0]  APB_M_pwdata;
      input  wire         APB_M_pwrite;
      
      input  wire [31:0]  APB_M2_paddr;
      input  wire         APB_M2_penable;
      output wire [31:0]  APB_M2_prdata;
      output wire [0:0]   APB_M2_pready;
      input  wire [0:0]   APB_M2_psel;
      output wire [0:0]   APB_M2_pslverr;
      input  wire [31:0]  APB_M2_pwdata;
      input  wire         APB_M2_pwrite;
      
      input  wire [31:0]  APB_M3_paddr;
      input  wire         APB_M3_penable;
      output wire [31:0]  APB_M3_prdata;
      output wire [0:0]   APB_M3_pready;
      input  wire [0:0]   APB_M3_psel;
      output wire [0:0]   APB_M3_pslverr;
      input  wire [31:0]  APB_M3_pwdata;
      input  wire         APB_M3_pwrite;
                  
      input wire pl_clk1;
      input wire pll_locked;
      input wire pl_clk2_300MHz;
      input wire pl_clk3_374MHz;
      input wire rst;
      
      wire [31:0] reg0;
      wire [31:0] reg1;
      wire [31:0] reg2;
      wire [31:0] reg3;
      wire [31:0] outreg0;
      wire [31:0] outreg1;
      wire [31:0] outreg2;
      wire [31:0] outreg3;
      wire [31:0] outreg4;
      wire [31:0] outreg5;
      wire [31:0] outreg6;
      wire [31:0] outreg7;
      
      wire clk;
                   
      //assign clk = pl_clk1_25MHz;       
      assign clk = pl_clk1;   
      
      
      assign outreg0 = 32'hab0de;
      assign outreg2 = reg0;//{16'b0, out_fixed_invsqrt};
      assign outreg3 = 32'hffff_ffff;
      assign outreg4 = 32'hffff_ffff;
      assign outreg5 = 32'hffff_ffff;
      assign outreg6 = 32'hffff_ffff;
      assign outreg7 = 32'hffff_ffff;
      
`include "vars.vh"
      
apb3_regbank   i_apb3_regbank   (
             .clk(clk),
             .rst_in(rst),
             .APB_M_paddr(APB_M_paddr),
             .APB_M_penable(APB_M_penable),
             .APB_M_psel(APB_M_psel),
             .APB_M_pwdata(APB_M_pwdata),
             .APB_M_pwrite(APB_M_pwrite),
             .APB_M_pready(APB_M_pready),
             .APB_M_prdata(APB_M_prdata),
             .APB_M_pslverr(APB_M_pslverr),
             .reg0(reg0),
             .reg1(reg1),
             .reg2(reg2),
             .reg3(reg3),
             .outreg0(outreg0), 
             .outreg1(outreg1),
             .outreg2(outreg2),
             .outreg3(outreg3),
             .outreg4(outreg4),
             .outreg5(outreg5),
             .outreg6(outreg6),
             .outreg7(outreg7)   
);
          

wire [15:0]  addra_rxram0;
wire [31:0] dina_rxram0;
wire [31:0] douta_rxram0;
wire        wea_rxram0;
wire        ena_rxram0;
wire [15:0]  addrb_rxram0;
wire [31:0] dinb_rxram0;
wire [31:0] doutb_rxram0;
wire        web_rxram0;
wire        enb_rxram0;

wire [15:0]  addra_rxram1;
wire [31:0] dina_rxram1;
wire [31:0] douta_rxram1;
wire        wea_rxram1;
wire        ena_rxram1;
wire [15:0]  addrb_rxram1;
wire [31:0] dinb_rxram1;
wire [31:0] doutb_rxram1;
wire        web_rxram1;
wire        enb_rxram1;

wire [15:0]  addra_txram0;
wire [31:0] dina_txram0;
wire [31:0] douta_txram0;
wire        wea_txram0;
wire        ena_txram0;
wire [15:0]  addrb_txram0;
wire [31:0] dinb_txram0;
wire [31:0] doutb_txram0;
wire        web_txram0;
wire        enb_txram0;

wire [15:0]  addra_txram1;
wire [31:0] dina_txram1;
wire [31:0] douta_txram1;
wire        wea_txram1;
wire        ena_txram1;
wire [15:0]  addrb_txram1;
wire [31:0] dinb_txram1;
wire [31:0] doutb_txram1;
wire        web_txram1;
wire        enb_txram1;

// just fix to this - port a for write and port b for read
xilinx_true_dual_port_write_first_2_clock_ram #( .RAM_DEPTH(`MAX_PARTICLES )) i_rxram_0 (
                    .addra(addra_rxram0),   // Port A address bus, width determined from RAM_DEPTH
                    .addrb(addrb_rxram0),   // Port B address bus, width determined from RAM_DEPTH
                    .dina(dina_rxram0),     // Port A RAM input data, width determined from RAM_WIDTH
                    .dinb(dinb_rxram0),     // Port B RAM input data, width determined from RAM_WIDTH
                    .clka(clk),     // Port A clock
                    .clkb(clk),     // Port B clock
                    .wea(wea_rxram0),       // Port A write enable
                    .web(web_rxram0),       // Port B write enable
                    .ena(ena_rxram0),       // Port A RAM Enable, for additional power savings, disable port when not in use
                    .enb(enb_rxram0),       // Port B RAM Enable, for additional power savings, disable port when not in use
                    .rsta(rst),     // Port A output reset (does not affect memory contents)
                    .rstb(rst),     // Port B output reset (does not affect memory contents)
                    .regcea(1'b1), // Port A output register enable
                    .regceb(1'b1), // Port B output register enable
                    .douta(douta_rxram0),   // Port A RAM output data, width determined from RAM_WIDTH
                    .doutb(doutb_rxram0)    // Port B RAM output data, width determined from RAM_WIDTH
        );
assign web_rxram0 = 1'b0; 

xilinx_true_dual_port_write_first_2_clock_ram #( .RAM_DEPTH(`MAX_PARTICLES )) i_rxram_1 (
                    .addra(addra_rxram1),   // Port A address bus, width determined from RAM_DEPTH
                    .addrb(addrb_rxram1),   // Port B address bus, width determined from RAM_DEPTH
                    .dina(dina_rxram1),     // Port A RAM input data, width determined from RAM_WIDTH
                    .dinb(dinb_rxram1),     // Port B RAM input data, width determined from RAM_WIDTH
                    .clka(clk),     // Port A clock
                    .clkb(clk),     // Port B clock
                    .wea(wea_rxram1),       // Port A write enable
                    .web(web_rxram1),       // Port B write enable
                    .ena(ena_rxram1),       // Port A RAM Enable, for additional power savings, disable port when not in use
                    .enb(enb_rxram1),       // Port B RAM Enable, for additional power savings, disable port when not in use
                    .rsta(rst),     // Port A output reset (does not affect memory contents)
                    .rstb(rst),     // Port B output reset (does not affect memory contents)
                    .regcea(1'b1), // Port A output register enable
                    .regceb(1'b1), // Port B output register enable
                    .douta(douta_rxram1),   // Port A RAM output data, width determined from RAM_WIDTH
                    .doutb(doutb_rxram1)    // Port B RAM output data, width determined from RAM_WIDTH
        );
assign web_rxram1 = 1'b0; 

xilinx_true_dual_port_write_first_2_clock_ram #( .RAM_DEPTH(`MAX_PARTICLES )) i_txram_0 (
                    .addra(addra_txram0),   // Port A address bus, width determined from RAM_DEPTH
                    .addrb(addrb_txram0),   // Port B address bus, width determined from RAM_DEPTH
                    .dina(dina_txram0),     // Port A RAM input data, width determined from RAM_WIDTH
                    .dinb(dinb_txram0),     // Port B RAM input data, width determined from RAM_WIDTH
                    .clka(clk),     // Port A clock
                    .clkb(clk),     // Port B clock
                    .wea(wea_txram0),       // Port A write enable
                    .web(web_txram0),       // Port B write enable
                    .ena(ena_txram0),       // Port A RAM Enable, for additional power savings, disable port when not in use
                    .enb(enb_txram0),       // Port B RAM Enable, for additional power savings, disable port when not in use
                    .rsta(rst),     // Port A output reset (does not affect memory contents)
                    .rstb(rst),     // Port B output reset (does not affect memory contents)
                    .regcea(1'b1), // Port A output register enable
                    .regceb(1'b1), // Port B output register enable
                    .douta(douta_txram0),   // Port A RAM output data, width determined from RAM_WIDTH
                    .doutb(doutb_txram0)    // Port B RAM output data, width determined from RAM_WIDTH
        );
        
assign web_txram0 = 1'b0; 

xilinx_true_dual_port_write_first_2_clock_ram #( .RAM_DEPTH(`MAX_PARTICLES )) i_txram_1 (
                    .addra(addra_txram1),   // Port A address bus, width determined from RAM_DEPTH
                    .addrb(addrb_txram1),   // Port B address bus, width determined from RAM_DEPTH
                    .dina(dina_txram1),     // Port A RAM input data, width determined from RAM_WIDTH
                    .dinb(dinb_txram1),     // Port B RAM input data, width determined from RAM_WIDTH
                    .clka(clk),     // Port A clock
                    .clkb(clk),     // Port B clock
                    .wea(wea_txram1),       // Port A write enable
                    .web(web_txram1),       // Port B write enable
                    .ena(ena_txram1),       // Port A RAM Enable, for additional power savings, disable port when not in use
                    .enb(enb_txram1),       // Port B RAM Enable, for additional power savings, disable port when not in use
                    .rsta(rst),     // Port A output reset (does not affect memory contents)
                    .rstb(rst),     // Port B output reset (does not affect memory contents)
                    .regcea(1'b1), // Port A output register enable
                    .regceb(1'b1), // Port B output register enable
                    .douta(douta_txram1),   // Port A RAM output data, width determined from RAM_WIDTH
                    .doutb(doutb_txram1)    // Port B RAM output data, width determined from RAM_WIDTH
        );
        
assign web_txram1 = 1'b0; 

apb3_bram_cntrl i_apb3_bram_cntrl(
                 .clk(clk),
                 .rst_in(rst),
                 .APB_M_paddr(APB_M2_paddr),
                 .APB_M_penable(APB_M2_penable),
                 .APB_M_psel(APB_M2_psel),
                 .APB_M_pwdata(APB_M2_pwdata),
                 .APB_M_pwrite(APB_M2_pwrite),
                 .APB_M_pready(APB_M2_pready),
                 .APB_M_prdata(APB_M2_prdata),
                 .APB_M_pslverr(APB_M2_pslverr),
                 
                 .APB_M2_paddr(APB_M3_paddr),
                 .APB_M2_penable(APB_M3_penable),
                 .APB_M2_psel(APB_M3_psel),
                 .APB_M2_pwdata(APB_M3_pwdata),
                 .APB_M2_pwrite(APB_M3_pwrite),
                 .APB_M2_pready(APB_M3_pready),
                 .APB_M2_prdata(APB_M3_prdata),
                 .APB_M2_pslverr(APB_M3_pslverr),
                 
                 // rx ram - write to this ram through sw 
                 // the following signals are generated from apb3 bram controller to write to rxram
                 .addra_rxram0(addra_rxram0),  
                 .dina_rxram0(dina_rxram0), 
                 .wea_rxram0(wea_rxram0), 
                 .ena_rxram0(ena_rxram0),
                 .douta_rxram0(douta_rxram0),  
                 
                 .addra_rxram1(addra_rxram1),  
                 .dina_rxram1(dina_rxram1), 
                 .wea_rxram1(wea_rxram1), 
                 .ena_rxram1(ena_rxram1),
                 .douta_rxram1(douta_rxram1),  
                 
                 // tx bram - read from this ram through sw
                 // the following signals are generated from apb3 bram controller to read from txram
                 .addrb_txram0(addrb_txram0),  
                 .enb_txram0(enb_txram0),
                 .doutb_txram0(doutb_txram0),
                 
                 .addrb_txram1(addrb_txram1),  
                 .enb_txram1(enb_txram1),
                 .doutb_txram1(doutb_txram1)  
                  
);

wire [15:0] timestep;
wire [15:0] softening_factor;
wire [15:0] num_of_bodies;

assign timestep = reg2[15:0];
assign softening_factor = reg3[15:0];
assign num_of_bodies = reg3[31:16];


`ifdef PARALLEL
        parallel_gravity_accelerator i_parallel_gravity_accelerator(
                     .clk(clk),
                     .rst_in(rst),
                     
                     // read from rxram 
                     .addrb_rxram0(addrb_rxram0),  
                     .enb_rxram0(enb_rxram0),
                     .doutb_rxram0(doutb_rxram0),  
                     
                     .addrb_rxram1(addrb_rxram1),  
                     .enb_rxram1(enb_rxram1),
                     .doutb_rxram1(doutb_rxram1),  
                     
                     // write to txram
                     .addra_txram0(addra_txram0),  
                     .dina_txram0(dina_txram0), 
                     .wea_txram0(wea_txram0), 
                     .ena_txram0(ena_txram0),
                     
                     .addra_txram1(addra_txram1),  
                     .dina_txram1(dina_txram1), 
                     .wea_txram1(wea_txram1), 
                     .ena_txram1(ena_txram1),
                     
                     //control in
                     .pll_locked(pll_locked),
                     .cntrl_reg0(reg0),
                     //status out
                     .status_reg0(outreg1),
                     .timestep(timestep),
                     .softening_factor(softening_factor),
                     .num_of_bodies(num_of_bodies)
                    );

`else
        gravity_accelerator i_gravity_accelerator(
                     .clk(clk),
                     .rst_in(rst),
                     
                     // read from rxram 
                     .addrb_rxram0(addrb_rxram0),  
                     .enb_rxram0(enb_rxram0),
                     .doutb_rxram0(doutb_rxram0),  
                     
                     .addrb_rxram1(addrb_rxram1),  
                     .enb_rxram1(enb_rxram1),
                     .doutb_rxram1(doutb_rxram1),  
                     
                     // write to txram
                     .addra_txram0(addra_txram0),  
                     .dina_txram0(dina_txram0), 
                     .wea_txram0(wea_txram0), 
                     .ena_txram0(ena_txram0),
                     
                     .addra_txram1(addra_txram1),  
                     .dina_txram1(dina_txram1), 
                     .wea_txram1(wea_txram1), 
                     .ena_txram1(ena_txram1),
                     
                     //control in
                     .pll_locked(pll_locked),
                     .cntrl_reg0(reg0),
                     //status out
                     .status_reg0(outreg1),
                     .timestep(timestep),
                     .softening_factor(softening_factor),
                     .num_of_bodies(num_of_bodies)
                    );
 `endif                   
    
endmodule

design_1.tcl

Tcl
Copy to <workspace>/src
##########################################################################
# 
#    Copyright 2019 Xilinx 
#
#    Licensed under the Apache License, Version 2.0 (the "License");
#    you may not use this file except in compliance with the License.
#    You may obtain a copy of the License at
# 
#      http://www.apache.org/licenses/LICENSE-2.0
# 
#    Unless required by applicable law or agreed to in writing, software
#    distributed under the License is distributed on an "AS IS" BASIS,
#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#    See the License for the specific language governing permissions and
#    limitations under the License.
# 
##########################################################################


################################################################
# This is a generated script based on design: design_1
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./nbody/nbodyproj.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project nbodyproj nbody -part xczu3eg-sbva484-1-i
}


# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_1

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
   return $nRet
}

set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
   set list_check_ips "\ 
xilinx.com:ip:axi_apb_bridge:3.0\
xilinx.com:ip:axi_uart16550:2.0\
xilinx.com:ip:clk_wiz:6.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:zynq_ultra_ps_e:3.2\
"

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 3
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder
  variable design_name

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set APB_M [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:apb_rtl:1.0 APB_M ]
  set APB_M2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:apb_rtl:1.0 APB_M2 ]
  set APB_M3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:apb_rtl:1.0 APB_M3 ]
  set gpio_sensors [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sensors ]
  set uart1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart1 ]

  # Create ports
  set bt_ctsn [ create_bd_port -dir I bt_ctsn ]
  set bt_rtsn [ create_bd_port -dir O bt_rtsn ]
  set peripheral_reset [ create_bd_port -dir O -from 0 -to 0 -type rst peripheral_reset ]
  set pl_clk1 [ create_bd_port -dir O -type clk pl_clk1 ]
  set pl_clk2_300MHz [ create_bd_port -dir O -type clk pl_clk2_300MHz ]
  set pl_clk3_374MHz [ create_bd_port -dir O -type clk pl_clk3_374MHz ]
  set pll_locked [ create_bd_port -dir O pll_locked ]
  set uart0_ctsn [ create_bd_port -dir I -type data uart0_ctsn ]
  set uart0_rtsn [ create_bd_port -dir O -type data uart0_rtsn ]
  set uart0_rxd [ create_bd_port -dir I uart0_rxd ]
  set uart0_txd [ create_bd_port -dir O uart0_txd ]

  # Create instance: axi_apb_bridge_0, and set properties
  set axi_apb_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_apb_bridge:3.0 axi_apb_bridge_0 ]
  set_property -dict [ list \
   CONFIG.C_APB_NUM_SLAVES {3} \
 ] $axi_apb_bridge_0

  # Create instance: axi_uart16550_0, and set properties
  set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ]
  set_property -dict [ list \
   CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999901} \
 ] $axi_uart16550_0

  # Create instance: clk_wiz_0, and set properties
  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
  set_property -dict [ list \
   CONFIG.CLKIN1_JITTER_PS {400.0} \
   CONFIG.CLKOUT1_DRIVES {BUFGCE} \
   CONFIG.CLKOUT1_JITTER {175.029} \
   CONFIG.CLKOUT1_PHASE_ERROR {222.305} \
   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
   CONFIG.CLKOUT2_DRIVES {BUFGCE} \
   CONFIG.CLKOUT3_DRIVES {BUFGCE} \
   CONFIG.CLKOUT4_DRIVES {BUFGCE} \
   CONFIG.CLKOUT5_DRIVES {BUFGCE} \
   CONFIG.CLKOUT6_DRIVES {BUFGCE} \
   CONFIG.CLKOUT7_DRIVES {BUFGCE} \
   CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
   CONFIG.MMCM_CLKFBOUT_MULT_F {48.000} \
   CONFIG.MMCM_CLKIN1_PERIOD {40.000} \
   CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
   CONFIG.MMCM_CLKOUT0_DIVIDE_F {6.000} \
   CONFIG.MMCM_DIVCLK_DIVIDE {1} \
   CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
   CONFIG.USE_PHASE_ALIGNMENT {true} \
   CONFIG.USE_SAFE_CLOCK_STARTUP {true} \
 ] $clk_wiz_0

  # Create instance: proc_sys_reset_0, and set properties
  set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]

  # Create instance: proc_sys_reset_1, and set properties
  set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]

  # Create instance: ps8_0_axi_periph, and set properties
  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
  set_property -dict [ list \
   CONFIG.NUM_MI {2} \
 ] $ps8_0_axi_periph

  # Create instance: zynq_ultra_ps_e_0, and set properties
  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 zynq_ultra_ps_e_0 ]
  set_property -dict [ list \
   CONFIG.CAN0_BOARD_INTERFACE {custom} \
   CONFIG.CAN1_BOARD_INTERFACE {custom} \
   CONFIG.CSU_BOARD_INTERFACE {custom} \
   CONFIG.DP_BOARD_INTERFACE {custom} \
   CONFIG.GEM0_BOARD_INTERFACE {custom} \
   CONFIG.GEM1_BOARD_INTERFACE {custom} \
   CONFIG.GEM2_BOARD_INTERFACE {custom} \
   CONFIG.GEM3_BOARD_INTERFACE {custom} \
   CONFIG.GPIO_BOARD_INTERFACE {custom} \
   CONFIG.IIC0_BOARD_INTERFACE {custom} \
   CONFIG.IIC1_BOARD_INTERFACE {custom} \
   CONFIG.NAND_BOARD_INTERFACE {custom} \
   CONFIG.PCIE_BOARD_INTERFACE {custom} \
   CONFIG.PJTAG_BOARD_INTERFACE {custom} \
   CONFIG.PMU_BOARD_INTERFACE {custom} \
   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
   CONFIG.PSU_IMPORT_BOARD_PRESET {} \
   CONFIG.PSU_MIO_0_DIRECTION {inout} \
   CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_0_SLEW {slow} \
   CONFIG.PSU_MIO_10_DIRECTION {inout} \
   CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_10_SLEW {slow} \
   CONFIG.PSU_MIO_11_DIRECTION {inout} \
   CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_11_SLEW {slow} \
   CONFIG.PSU_MIO_12_DIRECTION {inout} \
   CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_12_SLEW {slow} \
   CONFIG.PSU_MIO_13_DIRECTION {inout} \
   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_13_SLEW {slow} \
   CONFIG.PSU_MIO_14_DIRECTION {inout} \
   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_14_SLEW {slow} \
   CONFIG.PSU_MIO_15_DIRECTION {inout} \
   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_15_SLEW {slow} \
   CONFIG.PSU_MIO_16_DIRECTION {inout} \
   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_16_SLEW {slow} \
   CONFIG.PSU_MIO_17_DIRECTION {inout} \
   CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_17_SLEW {slow} \
   CONFIG.PSU_MIO_18_DIRECTION {inout} \
   CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_18_SLEW {slow} \
   CONFIG.PSU_MIO_19_DIRECTION {inout} \
   CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_19_SLEW {slow} \
   CONFIG.PSU_MIO_1_DIRECTION {inout} \
   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_1_SLEW {slow} \
   CONFIG.PSU_MIO_20_DIRECTION {inout} \
   CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_20_SLEW {slow} \
   CONFIG.PSU_MIO_21_DIRECTION {inout} \
   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_21_SLEW {slow} \
   CONFIG.PSU_MIO_22_DIRECTION {out} \
   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
   CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_22_SLEW {slow} \
   CONFIG.PSU_MIO_23_DIRECTION {inout} \
   CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_23_SLEW {slow} \
   CONFIG.PSU_MIO_24_DIRECTION {in} \
   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_24_SLEW {slow} \
   CONFIG.PSU_MIO_25_DIRECTION {inout} \
   CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_25_SLEW {slow} \
   CONFIG.PSU_MIO_26_DIRECTION {inout} \
   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_26_SLEW {slow} \
   CONFIG.PSU_MIO_27_DIRECTION {out} \
   CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_27_SLEW {slow} \
   CONFIG.PSU_MIO_28_DIRECTION {in} \
   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_28_SLEW {slow} \
   CONFIG.PSU_MIO_29_DIRECTION {out} \
   CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_29_SLEW {slow} \
   CONFIG.PSU_MIO_2_DIRECTION {in} \
   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_2_SLEW {slow} \
   CONFIG.PSU_MIO_30_DIRECTION {in} \
   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_30_SLEW {slow} \
   CONFIG.PSU_MIO_31_DIRECTION {inout} \
   CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_31_SLEW {slow} \
   CONFIG.PSU_MIO_32_DIRECTION {out} \
   CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_32_SLEW {slow} \
   CONFIG.PSU_MIO_33_DIRECTION {out} \
   CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_33_SLEW {slow} \
   CONFIG.PSU_MIO_34_DIRECTION {inout} \
   CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_34_SLEW {slow} \
   CONFIG.PSU_MIO_35_DIRECTION {inout} \
   CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_35_SLEW {slow} \
   CONFIG.PSU_MIO_36_DIRECTION {inout} \
   CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_36_SLEW {slow} \
   CONFIG.PSU_MIO_37_DIRECTION {inout} \
   CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_37_SLEW {slow} \
   CONFIG.PSU_MIO_38_DIRECTION {inout} \
   CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_38_SLEW {slow} \
   CONFIG.PSU_MIO_39_DIRECTION {inout} \
   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_39_SLEW {slow} \
   CONFIG.PSU_MIO_3_DIRECTION {out} \
   CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_3_SLEW {slow} \
   CONFIG.PSU_MIO_40_DIRECTION {inout} \
   CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_40_SLEW {slow} \
   CONFIG.PSU_MIO_41_DIRECTION {inout} \
   CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_41_SLEW {slow} \
   CONFIG.PSU_MIO_42_DIRECTION {inout} \
   CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_42_SLEW {slow} \
   CONFIG.PSU_MIO_43_DIRECTION {inout} \
   CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_43_SLEW {slow} \
   CONFIG.PSU_MIO_44_DIRECTION {inout} \
   CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_44_SLEW {slow} \
   CONFIG.PSU_MIO_45_DIRECTION {inout} \
   CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_45_SLEW {slow} \
   CONFIG.PSU_MIO_46_DIRECTION {inout} \
   CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_46_SLEW {slow} \
   CONFIG.PSU_MIO_47_DIRECTION {inout} \
   CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_47_SLEW {slow} \
   CONFIG.PSU_MIO_48_DIRECTION {inout} \
   CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_48_SLEW {slow} \
   CONFIG.PSU_MIO_49_DIRECTION {inout} \
   CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_49_SLEW {slow} \
   CONFIG.PSU_MIO_4_DIRECTION {inout} \
   CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_4_SLEW {slow} \
   CONFIG.PSU_MIO_50_DIRECTION {inout} \
   CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_50_SLEW {slow} \
   CONFIG.PSU_MIO_51_DIRECTION {out} \
   CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_51_SLEW {slow} \
   CONFIG.PSU_MIO_52_DIRECTION {in} \
   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_52_SLEW {slow} \
   CONFIG.PSU_MIO_53_DIRECTION {in} \
   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_53_SLEW {slow} \
   CONFIG.PSU_MIO_54_DIRECTION {inout} \
   CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_54_SLEW {slow} \
   CONFIG.PSU_MIO_55_DIRECTION {in} \
   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_55_SLEW {slow} \
   CONFIG.PSU_MIO_56_DIRECTION {inout} \
   CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_56_SLEW {slow} \
   CONFIG.PSU_MIO_57_DIRECTION {inout} \
   CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_57_SLEW {slow} \
   CONFIG.PSU_MIO_58_DIRECTION {out} \
   CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_58_SLEW {slow} \
   CONFIG.PSU_MIO_59_DIRECTION {inout} \
   CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_59_SLEW {slow} \
   CONFIG.PSU_MIO_5_DIRECTION {inout} \
   CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_5_SLEW {slow} \
   CONFIG.PSU_MIO_60_DIRECTION {inout} \
   CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_60_SLEW {slow} \
   CONFIG.PSU_MIO_61_DIRECTION {inout} \
   CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_61_SLEW {slow} \
   CONFIG.PSU_MIO_62_DIRECTION {inout} \
   CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_62_SLEW {slow} \
   CONFIG.PSU_MIO_63_DIRECTION {inout} \
   CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_63_SLEW {slow} \
   CONFIG.PSU_MIO_64_DIRECTION {in} \
   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_64_SLEW {slow} \
   CONFIG.PSU_MIO_65_DIRECTION {in} \
   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_65_SLEW {slow} \
   CONFIG.PSU_MIO_66_DIRECTION {inout} \
   CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_66_SLEW {slow} \
   CONFIG.PSU_MIO_67_DIRECTION {in} \
   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_67_SLEW {slow} \
   CONFIG.PSU_MIO_68_DIRECTION {inout} \
   CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_68_SLEW {slow} \
   CONFIG.PSU_MIO_69_DIRECTION {inout} \
   CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_69_SLEW {slow} \
   CONFIG.PSU_MIO_6_DIRECTION {inout} \
   CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_6_SLEW {slow} \
   CONFIG.PSU_MIO_70_DIRECTION {out} \
   CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_70_SLEW {slow} \
   CONFIG.PSU_MIO_71_DIRECTION {inout} \
   CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_71_SLEW {slow} \
   CONFIG.PSU_MIO_72_DIRECTION {inout} \
   CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_72_SLEW {slow} \
   CONFIG.PSU_MIO_73_DIRECTION {inout} \
   CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_73_SLEW {slow} \
   CONFIG.PSU_MIO_74_DIRECTION {inout} \
   CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_74_SLEW {slow} \
   CONFIG.PSU_MIO_75_DIRECTION {inout} \
   CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_75_SLEW {slow} \
   CONFIG.PSU_MIO_76_DIRECTION {inout} \
   CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_76_SLEW {slow} \
   CONFIG.PSU_MIO_77_DIRECTION {inout} \
   CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_77_SLEW {slow} \
   CONFIG.PSU_MIO_7_DIRECTION {inout} \
   CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_7_SLEW {slow} \
   CONFIG.PSU_MIO_8_DIRECTION {inout} \
   CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_8_SLEW {slow} \
   CONFIG.PSU_MIO_9_DIRECTION {inout} \
   CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
   CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \
   CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
   CONFIG.PSU_MIO_9_SLEW {slow} \
   CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
   CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
   CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
   CONFIG.PSU_SMC_CYCLE_T0 {NA} \
   CONFIG.PSU_SMC_CYCLE_T1 {NA} \
   CONFIG.PSU_SMC_CYCLE_T2 {NA} \
   CONFIG.PSU_SMC_CYCLE_T3 {NA} \
   CONFIG.PSU_SMC_CYCLE_T4 {NA} \
   CONFIG.PSU_SMC_CYCLE_T5 {NA} \
   CONFIG.PSU_SMC_CYCLE_T6 {NA} \
   CONFIG.PSU_VALUE_SILVERSION {3} \
   CONFIG.PSU__ACPU0__POWER__ON {1} \
   CONFIG.PSU__ACPU1__POWER__ON {1} \
   CONFIG.PSU__ACPU2__POWER__ON {1} \
   CONFIG.PSU__ACPU3__POWER__ON {1} \
   CONFIG.PSU__ACTUAL__IP {1} \
   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.332825} \
   CONFIG.PSU__AFI0_COHERENCY {0} \
   CONFIG.PSU__AFI1_COHERENCY {0} \
   CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
   CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
   CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
   CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.998901} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
   CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
   CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
   CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
   CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999756} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999756} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666412} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999451} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576017} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214418} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029297} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999451} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.999512} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \
   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
   CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
   CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999901} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.332825} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.333} \
   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.999512} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724087} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999512} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999756} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
   CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.998535} \
   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999901} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.999756} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \
   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999901} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.999512} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
   CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499817} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999901} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999695} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999634} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.499817} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.499817} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.499817} \
...

This file has been truncated, please download it to see its full contents.

Apache 2.0 license

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Apache License
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http://www.apache.org/licenses/

TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION

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END OF TERMS AND CONDITIONS

design_fixed_to_float.tcl

Tcl
Copy to <workspace>/src
##########################################################################
#    
#    Copyright 2019 Xilinx 
# 
#    Licensed under the Apache License, Version 2.0 (the "License");
#    you may not use this file except in compliance with the License.
#    You may obtain a copy of the License at
# 
#      http://www.apache.org/licenses/LICENSE-2.0
# 
#    Unless required by applicable law or agreed to in writing, software
#    distributed under the License is distributed on an "AS IS" BASIS,
#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#    See the License for the specific language governing permissions and
#    limitations under the License.
# 
##########################################################################


################################################################
# This is a generated script based on design: design_fixed_to_float
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_fixed_to_float_script.tcl

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project project_1 myproj -part xczu3eg-sbva484-1-i
}


# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_fixed_to_float

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
   return $nRet
}

set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
   set list_check_ips "\ 
xilinx.com:ip:floating_point:7.1\
"

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 3
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder
  variable design_name

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set M_AXIS_RESULT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_RESULT ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   ] $M_AXIS_RESULT
  set S_AXIS_A [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_A ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   CONFIG.HAS_TKEEP {0} \
   CONFIG.HAS_TLAST {0} \
   CONFIG.HAS_TREADY {0} \
   CONFIG.HAS_TSTRB {0} \
   CONFIG.LAYERED_METADATA {undef} \
   CONFIG.TDATA_NUM_BYTES {2} \
   CONFIG.TDEST_WIDTH {0} \
   CONFIG.TID_WIDTH {0} \
   CONFIG.TUSER_WIDTH {0} \
   ] $S_AXIS_A

  # Create ports
  set aclk [ create_bd_port -dir I -type clk aclk ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
 ] $aclk

  # Create instance: floating_point_0, and set properties
  set floating_point_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 ]
  set_property -dict [ list \
   CONFIG.A_Precision_Type {Custom} \
   CONFIG.C_A_Exponent_Width {16} \
   CONFIG.C_A_Fraction_Width {0} \
   CONFIG.C_Accum_Input_Msb {32} \
   CONFIG.C_Accum_Lsb {-31} \
   CONFIG.C_Accum_Msb {32} \
   CONFIG.C_Latency {1} \
   CONFIG.C_Mult_Usage {No_Usage} \
   CONFIG.C_Rate {1} \
   CONFIG.C_Result_Exponent_Width {8} \
   CONFIG.C_Result_Fraction_Width {19} \
   CONFIG.Flow_Control {NonBlocking} \
   CONFIG.Has_RESULT_TREADY {false} \
   CONFIG.Maximum_Latency {false} \
   CONFIG.Operation_Type {Fixed_to_float} \
   CONFIG.Result_Precision_Type {Custom} \
 ] $floating_point_0

  # Create interface connections
  connect_bd_intf_net -intf_net S_AXIS_A_1 [get_bd_intf_ports S_AXIS_A] [get_bd_intf_pins floating_point_0/S_AXIS_A]
  connect_bd_intf_net -intf_net floating_point_0_M_AXIS_RESULT [get_bd_intf_ports M_AXIS_RESULT] [get_bd_intf_pins floating_point_0/M_AXIS_RESULT]

  # Create port connections
  connect_bd_net -net aclk_1 [get_bd_ports aclk] [get_bd_pins floating_point_0/aclk]

  # Create address segments


  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""

design_float_to_fixed.tcl

Tcl
Copy to <workspace>/src
##########################################################################
#
#    Copyright 2019 Xilinx 
# 
#    Licensed under the Apache License, Version 2.0 (the "License");
#    you may not use this file except in compliance with the License.
#    You may obtain a copy of the License at
# 
#      http://www.apache.org/licenses/LICENSE-2.0
# 
#    Unless required by applicable law or agreed to in writing, software
#    distributed under the License is distributed on an "AS IS" BASIS,
#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#    See the License for the specific language governing permissions and
#    limitations under the License.
# 
##########################################################################


################################################################
# This is a generated script based on design: design_float_to_fixed
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_float_to_fixed_script.tcl

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project project_1 myproj -part xczu3eg-sbva484-1-i
}


# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_float_to_fixed

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
   return $nRet
}

set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
   set list_check_ips "\ 
xilinx.com:ip:floating_point:7.1\
"

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 3
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder
  variable design_name

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set M_AXIS_RESULT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_RESULT ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   ] $M_AXIS_RESULT
  set S_AXIS_A [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_A ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   CONFIG.HAS_TKEEP {0} \
   CONFIG.HAS_TLAST {0} \
   CONFIG.HAS_TREADY {0} \
   CONFIG.HAS_TSTRB {0} \
   CONFIG.LAYERED_METADATA {undef} \
   CONFIG.TDATA_NUM_BYTES {4} \
   CONFIG.TDEST_WIDTH {0} \
   CONFIG.TID_WIDTH {0} \
   CONFIG.TUSER_WIDTH {0} \
   ] $S_AXIS_A

  # Create ports
  set aclk [ create_bd_port -dir I -type clk aclk ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
 ] $aclk

  # Create instance: floating_point_0, and set properties
  set floating_point_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 ]
  set_property -dict [ list \
   CONFIG.A_Precision_Type {Custom} \
   CONFIG.C_A_Exponent_Width {8} \
   CONFIG.C_A_Fraction_Width {19} \
   CONFIG.C_Accum_Input_Msb {32} \
   CONFIG.C_Accum_Lsb {-31} \
   CONFIG.C_Accum_Msb {32} \
   CONFIG.C_Latency {1} \
   CONFIG.C_Mult_Usage {No_Usage} \
   CONFIG.C_Rate {1} \
   CONFIG.C_Result_Exponent_Width {16} \
   CONFIG.C_Result_Fraction_Width {0} \
   CONFIG.Flow_Control {NonBlocking} \
   CONFIG.Has_RESULT_TREADY {false} \
   CONFIG.Maximum_Latency {false} \
   CONFIG.Operation_Type {Float_to_fixed} \
   CONFIG.Result_Precision_Type {Custom} \
 ] $floating_point_0

  # Create interface connections
  connect_bd_intf_net -intf_net S_AXIS_A_1 [get_bd_intf_ports S_AXIS_A] [get_bd_intf_pins floating_point_0/S_AXIS_A]
  connect_bd_intf_net -intf_net floating_point_0_M_AXIS_RESULT [get_bd_intf_ports M_AXIS_RESULT] [get_bd_intf_pins floating_point_0/M_AXIS_RESULT]

  # Create port connections
  connect_bd_net -net aclk_1 [get_bd_ports aclk] [get_bd_pins floating_point_0/aclk]

  # Create address segments


  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""

design_fp_add.tcl

Tcl
Copy to <workspace>/src
##########################################################################
# 
#    Copyright 2019 Xilinx 
# 
#    Licensed under the Apache License, Version 2.0 (the "License");
#    you may not use this file except in compliance with the License.
#    You may obtain a copy of the License at
# 
#      http://www.apache.org/licenses/LICENSE-2.0
# 
#    Unless required by applicable law or agreed to in writing, software
#    distributed under the License is distributed on an "AS IS" BASIS,
#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#    See the License for the specific language governing permissions and
#    limitations under the License.
# 
##########################################################################


################################################################
# This is a generated script based on design: design_fp_add
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_fp_add_script.tcl

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project project_1 myproj -part xczu3eg-sbva484-1-i
}


# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_fp_add

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
   return $nRet
}

set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
   set list_check_ips "\ 
xilinx.com:ip:floating_point:7.1\
"

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 3
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder
  variable design_name

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set M_AXIS_RESULT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_RESULT ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   ] $M_AXIS_RESULT
  set S_AXIS_A [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_A ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   CONFIG.HAS_TKEEP {0} \
   CONFIG.HAS_TLAST {0} \
   CONFIG.HAS_TREADY {0} \
   CONFIG.HAS_TSTRB {0} \
   CONFIG.LAYERED_METADATA {undef} \
   CONFIG.TDATA_NUM_BYTES {4} \
   CONFIG.TDEST_WIDTH {0} \
   CONFIG.TID_WIDTH {0} \
   CONFIG.TUSER_WIDTH {0} \
   ] $S_AXIS_A
  set S_AXIS_B [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_B ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   CONFIG.HAS_TKEEP {0} \
   CONFIG.HAS_TLAST {0} \
   CONFIG.HAS_TREADY {0} \
   CONFIG.HAS_TSTRB {0} \
   CONFIG.LAYERED_METADATA {undef} \
   CONFIG.TDATA_NUM_BYTES {4} \
   CONFIG.TDEST_WIDTH {0} \
   CONFIG.TID_WIDTH {0} \
   CONFIG.TUSER_WIDTH {0} \
   ] $S_AXIS_B

  # Create ports
  set aclk [ create_bd_port -dir I -type clk aclk ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
 ] $aclk

  # Create instance: floating_point_0, and set properties
  set floating_point_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 ]
  set_property -dict [ list \
   CONFIG.A_Precision_Type {Custom} \
   CONFIG.Add_Sub_Value {Add} \
   CONFIG.C_A_Exponent_Width {8} \
   CONFIG.C_A_Fraction_Width {19} \
   CONFIG.C_Accum_Input_Msb {32} \
   CONFIG.C_Accum_Lsb {-31} \
   CONFIG.C_Accum_Msb {32} \
   CONFIG.C_Latency {3} \
   CONFIG.C_Mult_Usage {No_Usage} \
   CONFIG.C_Rate {1} \
   CONFIG.C_Result_Exponent_Width {8} \
   CONFIG.C_Result_Fraction_Width {19} \
   CONFIG.Flow_Control {NonBlocking} \
   CONFIG.Has_RESULT_TREADY {false} \
   CONFIG.Maximum_Latency {false} \
   CONFIG.Result_Precision_Type {Custom} \
 ] $floating_point_0

  # Create interface connections
  connect_bd_intf_net -intf_net S_AXIS_A_1 [get_bd_intf_ports S_AXIS_A] [get_bd_intf_pins floating_point_0/S_AXIS_A]
  connect_bd_intf_net -intf_net S_AXIS_B_1 [get_bd_intf_ports S_AXIS_B] [get_bd_intf_pins floating_point_0/S_AXIS_B]
  connect_bd_intf_net -intf_net floating_point_0_M_AXIS_RESULT [get_bd_intf_ports M_AXIS_RESULT] [get_bd_intf_pins floating_point_0/M_AXIS_RESULT]

  # Create port connections
  connect_bd_net -net aclk_1 [get_bd_ports aclk] [get_bd_pins floating_point_0/aclk]

  # Create address segments


  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""

design_fp_invsqrt.tcl

Tcl
Copy to <workspace>/src
##########################################################################
#
#    Copyright 2019 Xilinx 
# 
#    Licensed under the Apache License, Version 2.0 (the "License");
#    you may not use this file except in compliance with the License.
#    You may obtain a copy of the License at
# 
#      http://www.apache.org/licenses/LICENSE-2.0
# 
#    Unless required by applicable law or agreed to in writing, software
#    distributed under the License is distributed on an "AS IS" BASIS,
#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#    See the License for the specific language governing permissions and
#    limitations under the License.
# 
##########################################################################


################################################################
# This is a generated script based on design: design_fp_invsqrt
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_fp_invsqrt_script.tcl

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project project_1 myproj -part xczu3eg-sbva484-1-i
}


# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_fp_invsqrt

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
   return $nRet
}

set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
   set list_check_ips "\ 
xilinx.com:ip:floating_point:7.1\
"

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 3
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder
  variable design_name

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set M_AXIS_RESULT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_RESULT ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   ] $M_AXIS_RESULT
  set S_AXIS_A [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_A ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   CONFIG.HAS_TKEEP {0} \
   CONFIG.HAS_TLAST {0} \
   CONFIG.HAS_TREADY {0} \
   CONFIG.HAS_TSTRB {0} \
   CONFIG.LAYERED_METADATA {undef} \
   CONFIG.TDATA_NUM_BYTES {4} \
   CONFIG.TDEST_WIDTH {0} \
   CONFIG.TID_WIDTH {0} \
   CONFIG.TUSER_WIDTH {0} \
   ] $S_AXIS_A

  # Create ports
  set aclk [ create_bd_port -dir I -type clk aclk ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
 ] $aclk

  # Create instance: floating_point_0, and set properties
  set floating_point_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 ]
  set_property -dict [ list \
   CONFIG.A_Precision_Type {Single} \
   CONFIG.C_Latency {20} \
   CONFIG.C_Mult_Usage {Full_Usage} \
   CONFIG.C_Rate {1} \
   CONFIG.C_Result_Exponent_Width {8} \
   CONFIG.C_Result_Fraction_Width {24} \
   CONFIG.Flow_Control {NonBlocking} \
   CONFIG.Has_RESULT_TREADY {false} \
   CONFIG.Maximum_Latency {false} \
   CONFIG.Operation_Type {Rec_Square_Root} \
   CONFIG.Result_Precision_Type {Single} \
 ] $floating_point_0

  # Create interface connections
  connect_bd_intf_net -intf_net S_AXIS_A_1 [get_bd_intf_ports S_AXIS_A] [get_bd_intf_pins floating_point_0/S_AXIS_A]
  connect_bd_intf_net -intf_net floating_point_0_M_AXIS_RESULT [get_bd_intf_ports M_AXIS_RESULT] [get_bd_intf_pins floating_point_0/M_AXIS_RESULT]

  # Create port connections
  connect_bd_net -net aclk_1 [get_bd_ports aclk] [get_bd_pins floating_point_0/aclk]

  # Create address segments


  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""

design_fp_mult.tcl

Tcl
Copy to <workspace>/src
##########################################################################
# 
#    Copyright 2019 Xilinx 
#
#    Licensed under the Apache License, Version 2.0 (the "License");
#    you may not use this file except in compliance with the License.
#    You may obtain a copy of the License at
# 
#      http://www.apache.org/licenses/LICENSE-2.0
# 
#    Unless required by applicable law or agreed to in writing, software
#    distributed under the License is distributed on an "AS IS" BASIS,
#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#    See the License for the specific language governing permissions and
#    limitations under the License.
# 
##########################################################################


################################################################
# This is a generated script based on design: design_fp_mult
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source design_fp_mult_script.tcl

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project project_1 myproj -part xczu3eg-sbva484-1-i
}


# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_fp_mult

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
   return $nRet
}

set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
   set list_check_ips "\ 
xilinx.com:ip:floating_point:7.1\
"

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 3
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder
  variable design_name

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set M_AXIS_RESULT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_RESULT ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   ] $M_AXIS_RESULT
  set S_AXIS_A [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_A ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   CONFIG.HAS_TKEEP {0} \
   CONFIG.HAS_TLAST {0} \
   CONFIG.HAS_TREADY {0} \
   CONFIG.HAS_TSTRB {0} \
   CONFIG.LAYERED_METADATA {undef} \
   CONFIG.TDATA_NUM_BYTES {4} \
   CONFIG.TDEST_WIDTH {0} \
   CONFIG.TID_WIDTH {0} \
   CONFIG.TUSER_WIDTH {0} \
   ] $S_AXIS_A
  set S_AXIS_B [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_B ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
   CONFIG.HAS_TKEEP {0} \
   CONFIG.HAS_TLAST {0} \
   CONFIG.HAS_TREADY {0} \
   CONFIG.HAS_TSTRB {0} \
   CONFIG.LAYERED_METADATA {undef} \
   CONFIG.TDATA_NUM_BYTES {4} \
   CONFIG.TDEST_WIDTH {0} \
   CONFIG.TID_WIDTH {0} \
   CONFIG.TUSER_WIDTH {0} \
   ] $S_AXIS_B

  # Create ports
  set aclk [ create_bd_port -dir I -type clk aclk ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {10000000} \
 ] $aclk

  # Create instance: floating_point_0, and set properties
  set floating_point_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:floating_point:7.1 floating_point_0 ]
  set_property -dict [ list \
   CONFIG.A_Precision_Type {Custom} \
   CONFIG.C_A_Exponent_Width {8} \
   CONFIG.C_A_Fraction_Width {19} \
   CONFIG.C_Accum_Input_Msb {32} \
   CONFIG.C_Accum_Lsb {-31} \
   CONFIG.C_Accum_Msb {32} \
   CONFIG.C_Latency {2} \
   CONFIG.C_Mult_Usage {Max_Usage} \
   CONFIG.C_Rate {1} \
   CONFIG.C_Result_Exponent_Width {8} \
   CONFIG.C_Result_Fraction_Width {19} \
   CONFIG.Flow_Control {NonBlocking} \
   CONFIG.Has_RESULT_TREADY {false} \
   CONFIG.Maximum_Latency {false} \
   CONFIG.Operation_Type {Multiply} \
   CONFIG.Result_Precision_Type {Custom} \
 ] $floating_point_0

  # Create interface connections
  connect_bd_intf_net -intf_net S_AXIS_A_1 [get_bd_intf_ports S_AXIS_A] [get_bd_intf_pins floating_point_0/S_AXIS_A]
  connect_bd_intf_net -intf_net S_AXIS_B_1 [get_bd_intf_ports S_AXIS_B] [get_bd_intf_pins floating_point_0/S_AXIS_B]
  connect_bd_intf_net -intf_net floating_point_0_M_AXIS_RESULT [get_bd_intf_ports M_AXIS_RESULT] [get_bd_intf_pins floating_point_0/M_AXIS_RESULT]

  # Create port connections
  connect_bd_net -net aclk_1 [get_bd_ports aclk] [get_bd_pins floating_point_0/aclk]

  # Create address segments


  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""

gravity_accelerator.v

Verilog
Copy to <workspace>/src
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//    Copyright 2019 Xilinx
// 
//    Licensed under the Apache License, Version 2.0 (the "License");
//    you may not use this file except in compliance with the License.
//    You may obtain a copy of the License at
// 
//      http://www.apache.org/licenses/LICENSE-2.0
// 
//    Unless required by applicable law or agreed to in writing, software
//    distributed under the License is distributed on an "AS IS" BASIS,
//    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//    See the License for the specific language governing permissions and
//    limitations under the License.
// 
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx 
// Engineer: Rajeev Patwari
// 
// Create Date: 06/21/2018 12:38:19 PM
// Design Name: 
// Module Name: gravity_accelerator
// Project Name: ZZSoC Proj 2 Nbody sim
// Target Devices: XCZU3EG
// Tool Versions: 2018.3
// Description: 
//     Single gravity acceleartor engine to compute N body gravity equations
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//     All code designed, developed by me.
//     This module is Domain Specific Architecture with 1 N Body accelerator
//     ahieving maximum optimization by utilizing resources of ZU3EG
//     References:
//     1. N body problem exploration with GPU centric implementation 
//        https://developer.nvidia.com/gpugems/GPUGems3/gpugems3_ch31.html
// 	   2. Inspiration from Heterogenuos implementation paper which solves 
//        astronomical computations
//        https://academic.oup.com/pasj/article/55/6/1163/2056223  
//     3. FP_Add, FP_mult operate on 8 bit exponent and 19 bit mantissa (including sign)
//        This was chosen to efficiently utilize 1 DSP48 for multiplier as one 
//        multiplicand of DSP48 is only 18b wide. If FP32 is chosen, it would require
//        2 DSP48s to implement the macro. In case of FP_invsqrt, there is no customization 
//        option. Due to this, FP_invsqrt operated on FP32. Bit manipulation takes
//        care of data translation. All input and output data is stored in form
//        of int16 to plot directly to monitor.
//     
//////////////////////////////////////////////////////////////////////////////////

module gravity_accelerator(   
     input wire clk,
     input wire rst_in,
     // read from rxram 
    input wire [31:0]  doutb_rxram0, // data from rxram
    output wire [15:0]  addrb_rxram0, // bram_row_num to rxram - for reads
    output wire        enb_rxram0,
    
    input wire [31:0]  doutb_rxram1, // data from rxram
    output wire [15:0]  addrb_rxram1, // bram_row_num to rxram - for reads
    output wire        enb_rxram1,
        
    // write to txram
    output wire [31:0] dina_txram0,   // data to txram
    output wire [15:0]  addra_txram0, // bram_row_num to write to txram
    output wire        wea_txram0,   // write en - 1b per nibble
    output wire        ena_txram0,   // port enable
    
    output wire [31:0] dina_txram1,   // data to txram
    output wire [15:0]  addra_txram1, // bram_row_num to write to txram
    output wire        wea_txram1,   // write en - 1b per nibble
    output wire        ena_txram1,   // port enable
        
    //control in
    input wire [31:0]  cntrl_reg0,
    //status out
    output wire [31:0] status_reg0,
    input wire pll_locked,
    
    input wire [15:0] softening_factor,
    input wire [15:0] timestep,
    input wire [15:0] num_of_bodies
    
    );
    
    
    
    //--- wrires for 13 brams - description at the bottom of the module (prior to the instances
    wire [15:0] addra_ram_x;
    wire [26:0] dina_ram_x;
    wire [26:0] doutb_ram_x;
    wire [15:0] addrb_ram_x;
    wire wea_ram_x;
    wire enb_ram_x;
    
    wire [15:0] addra_ram_y;
    wire [26:0] dina_ram_y;
    wire [26:0] doutb_ram_y;
    wire [15:0] addrb_ram_y;
    wire wea_ram_y;
    wire enb_ram_y;
    
    wire [15:0] addra_ram_z;
    wire [26:0] dina_ram_z;
    wire [26:0] doutb_ram_z;
    wire [15:0] addrb_ram_z;
    wire wea_ram_z;
    wire enb_ram_z;
    
    wire [15:0] addra_ram_m;
    wire [26:0] dina_ram_m;
    wire [26:0] doutb_ram_m;
    wire [15:0] addrb_ram_m;
    wire wea_ram_m;
    wire enb_ram_m;
    
    wire [15:0] addra_ram_x_new;
    wire [26:0] dina_ram_x_new;
    wire [26:0] doutb_ram_x_new;
    wire [15:0] addrb_ram_x_new;
    wire wea_ram_x_new;
    wire ena_ram_x_new;
    wire enb_ram_x_new;
    
    wire [15:0] addra_ram_y_new;
    wire [26:0] dina_ram_y_new;
    wire [26:0] doutb_ram_y_new;
    wire [15:0] addrb_ram_y_new;
    wire wea_ram_y_new;
    wire ena_ram_y_new;
    wire enb_ram_y_new;
    
    wire [15:0] addra_ram_z_new;
    wire [26:0] dina_ram_z_new;
    wire [26:0] doutb_ram_z_new;
    wire [15:0] addrb_ram_z_new;
    wire wea_ram_z_new;
    wire ena_ram_z_new;
    wire enb_ram_z_new;
    
    wire [15:0] addra_ram_vx;
    wire [26:0] dina_ram_vx;
    wire [26:0] doutb_ram_vx;
    wire [15:0] addrb_ram_vx;
    wire wea_ram_vx;
    wire ena_ram_vx;
    wire enb_ram_vx;
    
    wire [15:0] addra_ram_vy;
    wire [26:0] dina_ram_vy;
    wire [26:0] doutb_ram_vy;
    wire [15:0] addrb_ram_vy;
    wire wea_ram_vy;
    wire ena_ram_vy;
    wire enb_ram_vy;
    wire [15:0] addra_ram_vz;
    wire [26:0] dina_ram_vz;
    wire [26:0] doutb_ram_vz;
    wire [15:0] addrb_ram_vz;
    wire wea_ram_vz;
    wire ena_ram_vz;
    wire enb_ram_vz;
    
    wire [15:0] addra_ram_accx;
    wire [26:0] dina_ram_accx;
    wire [26:0] doutb_ram_accx;
    wire [15:0] addrb_ram_accx;
    wire wea_ram_accx;
    wire ena_ram_accx;
    wire enb_ram_accx;
    
    wire [15:0] addra_ram_accy;
    wire [26:0] dina_ram_accy;
    wire [26:0] doutb_ram_accy;
    wire [15:0] addrb_ram_accy;
    wire wea_ram_accy;
    wire ena_ram_accy;
    wire enb_ram_accy;
    
    wire [15:0] addra_ram_accz;
    wire [26:0] dina_ram_accz;
    wire [26:0] doutb_ram_accz;
    wire [15:0] addrb_ram_accz;
    wire wea_ram_accz;
    wire ena_ram_accz;
    wire enb_ram_accz;
    
    
    // local reset pipeline - timing opt
    wire rst;
    reset_pipe rst_pipe_gravity_engine (.clk(clk), .rst_in(rst_in), .rst_out(rst));
    //assign rst = rst_in;
   
   
   // MAIN FSM states - one hot
   parameter S0  = 16'b0000_0000_0000_0001;
   parameter S1  = 16'b0000_0000_0000_0010;
   parameter S2  = 16'b0000_0000_0000_0100;
   parameter S3  = 16'b0000_0000_0000_1000;
   parameter S4  = 16'b0000_0000_0001_0000;
   parameter S5  = 16'b0000_0000_0010_0000;
   parameter S6  = 16'b0000_0000_0100_0000;
   parameter S7  = 16'b0000_0000_1000_0000;
   parameter S8  = 16'b0000_0001_0000_0000;
   parameter S9  = 16'b0000_0010_0000_0000;
   parameter S10 = 16'b0000_0100_0000_0000;
   parameter S11 = 16'b0000_1000_0000_0000;
   parameter S12 = 16'b0001_0000_0000_0000;
   parameter S13 = 16'b0010_0000_0000_0000;

   
   // internal signals generated by other logic, used by main fsm
   wire       main_fsm_start;
   assign main_fsm_start =  cntrl_reg0[0];
   reg        rxram_copy_done = 1'b0; 
   reg        gravity_engine_done= 1'b0;
   wire       txram_copy_done; 
   
   // internal signals generated by main fsm
   reg [15:0] current_state = S0;
   reg        main_fsm_done = 1'b0;
   reg        rxram_copy_start = 1'b0;
   reg        gravity_engine_start = 1'b0;
   reg [15:0] i_body_index = 16'b0;
   reg [15:0] j_body_index = 16'b0;
   reg        capture_new_x_in_txram = 1'b0;
   reg        index_select = 1'b0;
   reg        load_i_body = 1'b0;
   reg        reset_acceleration = 1'b0;
   reg        copy_txram_to_rxram_start = 1'b0;
   reg        copy_txram_to_rxram_done = 1'b0;
   
   
   assign status_reg0 = {pll_locked, 3'd0, rxram_copy_done, 3'd0, 23'd0, main_fsm_done};   
     
  // MAIN FSM  
   always @(posedge clk)
   begin
         case (current_state)
         
            S0 : begin // idle 16'h0001
               if (main_fsm_start)
                  current_state <= S1;
               else
                  current_state <= S0;
            end
         
            // S1 : convert every ram entry of rxram (x, y, z, m) from fixed(int16) to floating point
            //      and make a cpy of 27 bit x, y, z, m in local rams. trigger copy and wait for done
            S1 : begin  //16'h0002
               if (rxram_copy_done==1'b0)
                   rxram_copy_start <= 1'b1;
               current_state <= S2;
            end
         
            // wait for the rxram copy to be done
            S2 : begin //16'h0004
               if (rxram_copy_done)
                  begin
                    rxram_copy_start <= 1'b0;
                    current_state <= S3;
                    index_select <= 1'b0;
                  end  
               else
                  current_state <= S2;
            end
         
            //load x, y, z, m of ith body from ram to local var
            S3 : begin //16'h0008
               capture_new_x_in_txram <= 1'b0;
               reset_acceleration <= 1'b1;
               if (i_body_index < num_of_bodies)
                 begin
                  current_state <= S4;
                  index_select <= 1'b1;
                 end
               else
                  current_state <= S10;
            end
            
            S4: begin //16'h0010
                   load_i_body <= 1'b1;
                   reset_acceleration <= 1'b0;
                   current_state <= S5;
            end
            
            //load x, y, z, m of jth body from ram to local var
            S5 : begin //16'h0020
               index_select <= 1'b0;
               if (j_body_index < num_of_bodies)
                  current_state <= S6;
               else
                  begin
                     load_i_body <= 1'b0;
                     current_state <= S9;
                  end
            end

            // start gravity calculations for ith body w.r.t jth body
            S6: begin //16'h0040
               load_i_body <= 1'b0;
               gravity_engine_start <= 1'b1;
               current_state <= S7;
            end

            S7 : begin //16'h0080
               if (gravity_engine_done)
                 begin
                   current_state <= S8;
                   gravity_engine_start <= 1'b0;
                 end
               else
                  current_state <= S7;
            end
            
            S8 : begin //16'h0100
               j_body_index <= j_body_index + 16'b1;
               current_state <= S5;
            end
            
            // capture acc, vel, new x,y,z, reset j_body_index and go to next i
            S9: begin //16'h0200
               i_body_index <= i_body_index + 16'b1;
               j_body_index <= 16'b0;
               capture_new_x_in_txram <= 1'b1;
               current_state <= S3;
            end
            
            // all i's are done!!!
            // convert x,y,z,m floating point to fixed point and copy to txram in int16 
            S10: begin //16'h0400
               current_state <= S11;
            end
            
            // all new i data available in txram in fp. move this to rxram 
            S11: begin //16'h0800
                current_state <= S12;
                capture_new_x_in_txram <= 1'b0;
                copy_txram_to_rxram_start <= 1'b1;
            end
            
            // wait until the txram to rxram is done
            S12 : begin  ////16'h1000
               if (copy_txram_to_rxram_done==1'b1)
                 begin
                    current_state <= S13;
                    copy_txram_to_rxram_start <= 1'b0;
                    main_fsm_done <= 1'b1;
                  end
               else
                  current_state <= S12;
            end
         
           // wait until the main_fsm_done is acknowledged through sw and main_fsm_start is reset
            S13 : begin  ////16'h2000
               if (main_fsm_start ==1'b0)
                 begin
                    current_state <= S0;
                    main_fsm_done <= 1'b0;
                    i_body_index <= 16'b0;
                    j_body_index <= 16'b0;
                  end
               else
                  current_state <= S13;
            end
         
            // Fault Recovery
            default : begin  
                current_state <= S0;
            end
         endcase
   end
   
   // as soon as gravity accelerator starts, run the counter
   reg [31:0] gravity_counter; // on ehot bit shift to count cycles
   always@(posedge clk)
   begin
       if (rst)
         begin
           gravity_counter <= 32'b1;
           gravity_engine_done <= 1'b0;
         end
       else
         begin
             if ((gravity_engine_done == 1'b0) && (gravity_engine_start == 1'b1))
                 begin
                   if (gravity_counter == 32'd45) // wait for 45 clock cycles to get result
                     gravity_engine_done <= 32'b1;
                   else
                     gravity_counter <= gravity_counter + 32'b1;
                 end
             else if ((gravity_engine_done == 1'b1) && (gravity_engine_start == 1'b0))
                 begin
                     gravity_engine_done <= 1'b0;
                     gravity_counter <= 32'b1;
                 end
         end  
   end 						
   
   assign addrb_ram_x = (index_select) ? i_body_index : j_body_index;
   assign addrb_ram_y = (index_select) ? i_body_index : j_body_index;
   assign addrb_ram_z = (index_select) ? i_body_index : j_body_index;
   assign addrb_ram_m = (index_select) ? i_body_index : j_body_index;
   
   // rxram copy - triggered by setting rxram_copy_start in S1 of main FSM,
   reg [15:0] ram_counter = 16'b0;
   reg [15:0] ram_counter_delayed = 16'b0;
   reg [15:0] ram_counter_delayed2 = 16'b0;
   reg [15:0] ram_counter_delayed3 = 16'b0;
   always@(posedge clk)
   begin
           ram_counter_delayed <= ram_counter;
           ram_counter_delayed2 <= ram_counter_delayed;
           ram_counter_delayed3 <= ram_counter_delayed2;
           if ((rxram_copy_done == 1'b0) && (rxram_copy_start == 1'b1))
             begin
               if (ram_counter_delayed3 == num_of_bodies)
                 begin
                  rxram_copy_done <= 1'b1;
                  ram_counter <= 16'd0;
                 end
               else
                  ram_counter <= ram_counter + 1'b1;
              end
           else if ((copy_txram_to_rxram_done == 1'b0) &&(copy_txram_to_rxram_start == 1'b1))
             begin
               if (ram_counter == num_of_bodies)
                  begin
                   copy_txram_to_rxram_done <= 1'b1;
                   ram_counter <= 16'd0;
                 end
               else
                  ram_counter <= ram_counter + 1'b1;
              end
            else if (main_fsm_done)
              begin
                copy_txram_to_rxram_done <= 1'b0;
              end
   end 						
		
    // fixed to float - this is S1 of main FSM
    wire [26:0] wire_x_body_fp, wire_y_body_fp, wire_z_body_fp, wire_m_body_fp;
    wire        wire_x_body_fp_valid, wire_y_body_fp_valid, wire_z_body_fp_valid, wire_m_body_fp_valid; 
    design_fixed_to_float_wrapper i_fixed_to_float_x    (.M_AXIS_RESULT_tdata(wire_x_body_fp), .M_AXIS_RESULT_tvalid(wire_x_body_fp_valid), .S_AXIS_A_tdata(doutb_rxram0[31:16]), .S_AXIS_A_tvalid(1'b1), .aclk(clk));  
    design_fixed_to_float_wrapper i_fixed_to_float_y    (.M_AXIS_RESULT_tdata(wire_y_body_fp), .M_AXIS_RESULT_tvalid(wire_y_body_fp_valid), .S_AXIS_A_tdata(doutb_rxram0[15:0]),  .S_AXIS_A_tvalid(1'b1), .aclk(clk));  
    design_fixed_to_float_wrapper i_fixed_to_float_z    (.M_AXIS_RESULT_tdata(wire_z_body_fp), .M_AXIS_RESULT_tvalid(wire_z_body_fp_valid), .S_AXIS_A_tdata(doutb_rxram1[31:16]), .S_AXIS_A_tvalid(1'b1), .aclk(clk));  
    design_fixed_to_float_wrapper i_fixed_to_float_mass (.M_AXIS_RESULT_tdata(wire_m_body_fp), .M_AXIS_RESULT_tvalid(wire_m_body_fp_valid), .S_AXIS_A_tdata(doutb_rxram1[15:0]),  .S_AXIS_A_tvalid(1'b1), .aclk(clk));  
                                    
    // fp27 rxrams from gravity engine (bottom of this module)
    assign addra_ram_x = (rxram_copy_start) ? ram_counter_delayed3: ram_counter_delayed2;
    assign dina_ram_x  = (copy_txram_to_rxram_start) ? doutb_ram_x_new : wire_x_body_fp;
    assign enb_ram_x   = (~rxram_copy_start) || (load_i_body) || (~copy_txram_to_rxram_start); 
    assign wea_ram_x   = rxram_copy_start || copy_txram_to_rxram_start; 
    
    assign addra_ram_y = (rxram_copy_start) ? ram_counter_delayed3: ram_counter_delayed2;
    assign dina_ram_y  = (copy_txram_to_rxram_start) ? doutb_ram_y_new : wire_y_body_fp; 
    assign enb_ram_y   = (~rxram_copy_start) || (load_i_body) || (~copy_txram_to_rxram_start);
    assign wea_ram_y   = rxram_copy_start || copy_txram_to_rxram_start; 
    
    assign addra_ram_z = (rxram_copy_start) ? ram_counter_delayed3: ram_counter_delayed2;
    assign dina_ram_z  = (copy_txram_to_rxram_start) ? doutb_ram_z_new : wire_z_body_fp;
    assign enb_ram_z   = (~rxram_copy_start) || (load_i_body) || (~copy_txram_to_rxram_start);
    assign wea_ram_z   = rxram_copy_start || copy_txram_to_rxram_start; 
    
    assign addra_ram_m = (rxram_copy_start) ? ram_counter_delayed3: ram_counter_delayed2;
    assign dina_ram_m  = wire_m_body_fp; 
    assign enb_ram_m   = (~rxram_copy_start) || (load_i_body);
    assign wea_ram_m   = rxram_copy_start ; 
    
    // int16 rxrams from compute engine
    assign enb_rxram0   = rxram_copy_start;
    assign addrb_rxram0 = ram_counter;
    assign enb_rxram1   = rxram_copy_start;
    assign addrb_rxram1 = ram_counter ;
        
    // save velocity nd acceleration at the end of the iteration
    wire [26:0] acc_x, acc_y, acc_z;
    wire [26:0] vx_new_fp, vy_new_fp, vz_new_fp;
    
    assign addra_ram_accx = i_body_index;
    assign dina_ram_accx  = acc_x ; 
    assign enb_ram_accx   = ~gravity_engine_done ; // avoid write collision
    assign wea_ram_accx   = gravity_engine_done ; 
    assign addrb_ram_accx = i_body_index;
    
    assign addra_ram_accy = i_body_index;
    assign dina_ram_accy  = acc_y ; 
    assign enb_ram_accy   = ~gravity_engine_done ; // avoid write collision
    assign wea_ram_accy   = gravity_engine_done ; 
    assign addrb_ram_accy = i_body_index;
    
    assign addra_ram_accz = i_body_index;
    assign dina_ram_accz  = acc_z ; 
    assign enb_ram_accz   = ~gravity_engine_done ; // avoid write collision
    assign wea_ram_accz   = gravity_engine_done ; 
    assign addrb_ram_accz = i_body_index;
             
    assign addra_ram_vx = i_body_index;
    assign dina_ram_vx  = vx_new_fp ; 
    assign enb_ram_vx   = ~gravity_engine_done ; // avoid write collision
    assign wea_ram_vx   = gravity_engine_done ; 
    assign addrb_ram_vx = i_body_index;
    
    assign addra_ram_vy = i_body_index;
    assign dina_ram_vy  = vy_new_fp ; 
    assign enb_ram_vy   = ~gravity_engine_done ; // avoid write collision
    assign wea_ram_vy   = gravity_engine_done ; 
    assign addrb_ram_vy = i_body_index;
    
    assign addra_ram_vz = i_body_index;
    assign dina_ram_vz  = vz_new_fp ; 
    assign enb_ram_vz   = ~gravity_engine_done ; // avoid write collision
    assign wea_ram_vz   = gravity_engine_done ; 
    assign addrb_ram_vz = i_body_index;

    // Capture ith body data from ram_x,ram_y,ram_z, ram_m and ram_vx, vy, vz
    reg [26:0] i_body_x_fp, i_body_y_fp, i_body_z_fp, i_body_mass_fp;    
    reg [26:0] i_body_vx_fp, i_body_vy_fp, i_body_vz_fp;
          
    always@(posedge clk)
    begin
        if (rst)
           begin
             i_body_x_fp    <= 27'd0;
             i_body_y_fp    <= 27'd0;
             i_body_z_fp    <= 27'd0;
             i_body_mass_fp <= 27'd0;
             i_body_vx_fp   <= 27'd0;
             i_body_vy_fp   <= 27'd0;
             i_body_vz_fp   <= 27'd0;
           end
        else
           begin
             if ( load_i_body )
                 begin
                     i_body_x_fp    <= doutb_ram_x;
                     i_body_y_fp    <= doutb_ram_y;
                     i_body_z_fp    <= doutb_ram_z;
                     i_body_mass_fp <= doutb_ram_m;
                     i_body_vx_fp   <= doutb_ram_vx;
                     i_body_vy_fp   <= doutb_ram_vy;
                     i_body_vz_fp   <= doutb_ram_vz;
                 end
           end
    end


    // as soon as gravity_engine_start is triggered, compute the equation/ this takes multiple clock cycles
    // use a counter and trigger done as needed
    // at this moment, i_body_x,y,z,m has ith data and doutb_ram_x,y,z,m has jth body data
    wire [26:0] j_body_x_fp, j_body_y_fp, j_body_z_fp, j_body_mass_fp;
    assign j_body_x_fp    = doutb_ram_x;
    assign j_body_y_fp    = doutb_ram_y;
    assign j_body_z_fp    = doutb_ram_z;
    assign j_body_mass_fp = doutb_ram_m;
     
    // step 1: all adds in parallel   - latency 
    wire [26:0] negative_i_body_x_fp, negative_i_body_y_fp, negative_i_body_z_fp;
    wire [26:0] ij_body_rx_fp, ij_body_ry_fp, ij_body_rz_fp;
    wire        ij_body_rx_fp_valid, ij_body_ry_fp_valid, ij_body_rz_fp_valid;
    assign negative_i_body_x_fp = {~i_body_x_fp[26], i_body_x_fp[25:0]};            
    assign negative_i_body_y_fp = {~i_body_y_fp[26], i_body_y_fp[25:0]};            
    assign negative_i_body_z_fp = {~i_body_z_fp[26], i_body_z_fp[25:0]};            
    design_fp_add_wrapper step1_rx_add (.M_AXIS_RESULT_tdata(ij_body_rx_fp), .M_AXIS_RESULT_tvalid(ij_body_rx_fp_valid), .S_AXIS_A_tdata(j_body_x_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(negative_i_body_x_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk));
    design_fp_add_wrapper step1_ry_add (.M_AXIS_RESULT_tdata(ij_body_ry_fp), .M_AXIS_RESULT_tvalid(ij_body_ry_fp_valid), .S_AXIS_A_tdata(j_body_y_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(negative_i_body_y_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk));
    design_fp_add_wrapper step1_rz_add (.M_AXIS_RESULT_tdata(ij_body_rz_fp), .M_AXIS_RESULT_tvalid(ij_body_rz_fp_valid), .S_AXIS_A_tdata(j_body_z_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(negative_i_body_z_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk));
    
    // step 2: all mults in parallel - - latency 
    wire [26:0] ij_body_rx2_fp, ij_body_ry2_fp, ij_body_rz2_fp;
    wire        ij_body_rx2_fp_valid, ij_body_ry2_fp_valid, ij_body_rz2_fp_valid;
    wire [26:0] softening_factor_fp, softening_factor_fp2;
    wire        softening_factor_fp_valid, softening_factor_fp2_valid;
    //assign softening_factor = 16'd1500;    // softening factor - cuzz G=1 - what is this? parallel universe where everything is 6.67 x 10e+23 times worse ??
                                         // decided to connect to apb reg
    design_fp_mult_wrapper step2_fp_mult_rx2 (.M_AXIS_RESULT_tdata(ij_body_rx2_fp), .M_AXIS_RESULT_tvalid(ij_body_rx2_fp_valid), .S_AXIS_A_tdata(ij_body_rx_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(ij_body_rx_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step2_fp_mult_ry2 (.M_AXIS_RESULT_tdata(ij_body_ry2_fp), .M_AXIS_RESULT_tvalid(ij_body_ry2_fp_valid), .S_AXIS_A_tdata(ij_body_ry_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(ij_body_ry_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step2_fp_mult_rz2 (.M_AXIS_RESULT_tdata(ij_body_rz2_fp), .M_AXIS_RESULT_tvalid(ij_body_rz2_fp_valid), .S_AXIS_A_tdata(ij_body_rz_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(ij_body_rz_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    // the next 2 are sequential
    design_fixed_to_float_wrapper j_fixed_to_float_sf    (.M_AXIS_RESULT_tdata(softening_factor_fp), .M_AXIS_RESULT_tvalid(softening_factor_fp_valid), .S_AXIS_A_tdata(softening_factor), .S_AXIS_A_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step2_fp_mult_sf2 (.M_AXIS_RESULT_tdata(softening_factor_fp2), .M_AXIS_RESULT_tvalid(softening_factor_fp2_valid), .S_AXIS_A_tdata(softening_factor_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(softening_factor_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    
    //step 3:  latency
    wire [26:0] step3_fp0, step3_fp1;
    wire        step3_fp0_valid, step3_fp1_valid;
    
    design_fp_add_wrapper step3_add0 (.M_AXIS_RESULT_tdata(step3_fp0), .M_AXIS_RESULT_tvalid(step3_fp0_valid), .S_AXIS_A_tdata(ij_body_rx2_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(ij_body_ry2_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk));       
    design_fp_add_wrapper step3_add1 (.M_AXIS_RESULT_tdata(step3_fp1), .M_AXIS_RESULT_tvalid(step3_fp1_valid), .S_AXIS_A_tdata(ij_body_rz2_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(softening_factor_fp2), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    
    // step 4  latency
    //wire        underflow_step4;
    wire [26:0] step4_fp1;
    wire        step4_fp1_valid;
    design_fp_add_wrapper step4_add0 (.M_AXIS_RESULT_tdata(step4_fp1), .M_AXIS_RESULT_tvalid(step4_fp1_valid), .S_AXIS_A_tdata(step3_fp0), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(step3_fp1), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
   
    // step 5:  latency 
    //wire        underflow_step5;
    wire [26:0] step5_fp0;
    wire        step5_fp0_valid;
    design_fp_mult_wrapper step5_mult0 (.M_AXIS_RESULT_tdata(step5_fp0), .M_AXIS_RESULT_tvalid(step5_fp0_valid), .S_AXIS_A_tdata(step4_fp1), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(step4_fp1), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
      
    // step 6:  latency 
    wire        underflow_step6;
    wire [26:0] d_cubed;
    wire         d_cubed_valid;
    design_fp_mult_wrapper step6_mult0 (.M_AXIS_RESULT_tdata(d_cubed), .M_AXIS_RESULT_tvalid(d_cubed_valid), .S_AXIS_A_tdata(step4_fp1), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(step5_fp0), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
      
    // step 7:  latency 
    // fast inverse square root is  pipelined 
	// fast inverse is FP32 while allother FP are FP27.
    wire [31:0] inv_sqrt_fp;
    wire        inv_sqrt_fp_valid;
    design_fp_invsqrt_wrapper  step7_fast_inv_sqrt (.M_AXIS_RESULT_tdata(inv_sqrt_fp), .M_AXIS_RESULT_tvalid(inv_sqrt_fp_valid), .S_AXIS_A_tdata({d_cubed, 5'b0}), .S_AXIS_A_tvalid(1'b1), .aclk(clk)); 
     
    // step 8:  latency
    wire [26:0] s_fp;
    wire        s_fp_valid;
    design_fp_mult_wrapper step8_multx (.M_AXIS_RESULT_tdata(s_fp), .M_AXIS_RESULT_tvalid(s_fp_valid), .S_AXIS_A_tdata(inv_sqrt_fp[31:5]), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(j_body_mass_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    
    // step 9:  latency 
    reg [26:0]  acceleration_i_x, acceleration_i_y, acceleration_i_z;                      
    wire [26:0] acc_ij_x, acc_ij_y, acc_ij_z;
    wire        acc_ij_x_valid, acc_ij_y_valid, acc_ij_z_valid;
    design_fp_mult_wrapper step9_accx (.M_AXIS_RESULT_tdata(acc_ij_x), .M_AXIS_RESULT_tvalid(acc_ij_x_valid), .S_AXIS_A_tdata(ij_body_rx_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(s_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step9_accy (.M_AXIS_RESULT_tdata(acc_ij_y), .M_AXIS_RESULT_tvalid(acc_ij_y_valid), .S_AXIS_A_tdata(ij_body_ry_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(s_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step9_accz (.M_AXIS_RESULT_tdata(acc_ij_z), .M_AXIS_RESULT_tvalid(acc_ij_z_valid), .S_AXIS_A_tdata(ij_body_rz_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(s_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
   
    // step 10:  latency 
    wire         acc_x_valid, acc_y_valid, acc_z_valid;
    design_fp_add_wrapper step10_addx (.M_AXIS_RESULT_tdata(acc_x), .M_AXIS_RESULT_tvalid(acc_x_valid), .S_AXIS_A_tdata(acc_ij_x), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(acceleration_i_x), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_add_wrapper step10_addy (.M_AXIS_RESULT_tdata(acc_y), .M_AXIS_RESULT_tvalid(acc_y_valid), .S_AXIS_A_tdata(acc_ij_y), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(acceleration_i_y), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_add_wrapper step10_addz (.M_AXIS_RESULT_tdata(acc_z), .M_AXIS_RESULT_tvalid(acc_z_valid), .S_AXIS_A_tdata(acc_ij_z), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(acceleration_i_z), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
   
    // step 11:  latency 
    wire [26:0] timestep_fp;
    wire        timestep_fp_valid;
    
    wire [26:0] vx_times_t_fp, vy_times_t_fp, vz_times_t_fp;
    wire        vx_times_t_fp_valid, vy_times_t_fp_valid, vz_times_t_fp_valid;
    wire [26:0] acc_x_times_t_fp, acc_y_times_t_fp, acc_z_times_t_fp;
    wire        acc_x_times_t_fp_valid, acc_y_times_t_fp_valid, acc_z_times_t_fp_valid;
    
    design_fixed_to_float_wrapper j_fixed_to_float_ts    (.M_AXIS_RESULT_tdata(timestep_fp), .M_AXIS_RESULT_tvalid(timestep_fp_valid), .S_AXIS_A_tdata(timestep), .S_AXIS_A_tvalid(1'b1), .aclk(clk)); 
            
    design_fp_mult_wrapper step11_vtx (.M_AXIS_RESULT_tdata(vx_times_t_fp), .M_AXIS_RESULT_tvalid(vx_times_t_fp_valid), .S_AXIS_A_tdata(i_body_vx_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(timestep_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step11_vty (.M_AXIS_RESULT_tdata(vy_times_t_fp), .M_AXIS_RESULT_tvalid(vy_times_t_fp_valid), .S_AXIS_A_tdata(i_body_vy_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(timestep_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step11_vtz (.M_AXIS_RESULT_tdata(vz_times_t_fp), .M_AXIS_RESULT_tvalid(vz_times_t_fp_valid), .S_AXIS_A_tdata(i_body_vz_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(timestep_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    
    design_fp_mult_wrapper step11_atx (.M_AXIS_RESULT_tdata(acc_x_times_t_fp), .M_AXIS_RESULT_tvalid(acc_x_times_t_fp_valid), .S_AXIS_A_tdata(acceleration_i_x), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(timestep_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step11_aty (.M_AXIS_RESULT_tdata(acc_y_times_t_fp), .M_AXIS_RESULT_tvalid(acc_y_times_t_fp_valid), .S_AXIS_A_tdata(acceleration_i_y), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(timestep_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_mult_wrapper step11_atz (.M_AXIS_RESULT_tdata(acc_z_times_t_fp), .M_AXIS_RESULT_tvalid(acc_z_times_t_fp_valid), .S_AXIS_A_tdata(acceleration_i_z), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(timestep_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    
    
    // step 12:  latency 
    wire [26:0] x_new_fp, y_new_fp, z_new_fp;        
    wire        x_new_fp_valid, y_new_fp_valid, z_new_fp_valid;        
    design_fp_add_wrapper step12_newx  (.M_AXIS_RESULT_tdata(x_new_fp), .M_AXIS_RESULT_tvalid(x_new_fp_valid), .S_AXIS_A_tdata(vx_times_t_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(i_body_x_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_add_wrapper step12_newy  (.M_AXIS_RESULT_tdata(y_new_fp), .M_AXIS_RESULT_tvalid(y_new_fp_valid), .S_AXIS_A_tdata(vy_times_t_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(i_body_y_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_add_wrapper step12_newz  (.M_AXIS_RESULT_tdata(z_new_fp), .M_AXIS_RESULT_tvalid(z_new_fp_valid), .S_AXIS_A_tdata(vz_times_t_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(i_body_z_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    
    wire vx_new_fp_valid, vy_new_fp_valid, vz_new_fp_valid;
    design_fp_add_wrapper step12_newvx (.M_AXIS_RESULT_tdata(vx_new_fp), .M_AXIS_RESULT_tvalid(vx_new_fp_valid), .S_AXIS_A_tdata(acc_x_times_t_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(i_body_vx_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_add_wrapper step12_newvy (.M_AXIS_RESULT_tdata(vy_new_fp), .M_AXIS_RESULT_tvalid(vy_new_fp_valid), .S_AXIS_A_tdata(acc_y_times_t_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(i_body_vy_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    design_fp_add_wrapper step12_newvz (.M_AXIS_RESULT_tdata(vz_new_fp), .M_AXIS_RESULT_tvalid(vz_new_fp_valid), .S_AXIS_A_tdata(acc_z_times_t_fp), .S_AXIS_A_tvalid(1'b1), .S_AXIS_B_tdata(i_body_vz_fp), .S_AXIS_B_tvalid(1'b1), .aclk(clk)); 
    
	// step 13: latency 0 tck
    wire [15:0] doutb_ram_x_new_int, doutb_ram_y_new_int, doutb_ram_z_new_int;
    wire        doutb_ram_x_new_int_valid, doutb_ram_y_new_int_valid, doutb_ram_z_new_int_valid;
    design_float_to_fixed_wrapper step13_new_x  (.M_AXIS_RESULT_tdata(doutb_ram_x_new_int), .M_AXIS_RESULT_tvalid(doutb_ram_x_new_int_valid), .S_AXIS_A_tdata(x_new_fp), .S_AXIS_A_tvalid(1'b1), .aclk(clk)); 
    design_float_to_fixed_wrapper step13_new_y  (.M_AXIS_RESULT_tdata(doutb_ram_y_new_int), .M_AXIS_RESULT_tvalid(doutb_ram_y_new_int_valid), .S_AXIS_A_tdata(y_new_fp), .S_AXIS_A_tvalid(1'b1), .aclk(clk)); 
    design_float_to_fixed_wrapper step13_new_z  (.M_AXIS_RESULT_tdata(doutb_ram_z_new_int), .M_AXIS_RESULT_tvalid(doutb_ram_z_new_int_valid), .S_AXIS_A_tdata(z_new_fp), .S_AXIS_A_tvalid(1'b1), .aclk(clk)); 
    
    always@(posedge clk)
    begin
       if (rst)
          begin
            acceleration_i_x <= 27'd0;
            acceleration_i_y <= 27'd0;
            acceleration_i_z <= 27'd0;
          end
       else
          begin
            if ((gravity_engine_done) && (i_body_index != j_body_index)) // make sure this is associated with pipeline 7 output (before flop)
                begin
                    acceleration_i_x    <= acc_x; // new acceletation_i_x is availale
                    acceleration_i_y    <= acc_y;
                    acceleration_i_z    <= acc_z;
                end
            else if (reset_acceleration)
                begin
                    acceleration_i_x    <= 27'b0; // new acceletation_i_x is availale
                    acceleration_i_y    <= 27'b0;
                    acceleration_i_z    <= 27'b0;
                end
          end
    end 
    
    reg [15:0] i_body_index_delayed=16'b0;
    reg [15:0] i_body_index_delayed1=16'b0;
    always@(posedge clk) begin
      i_body_index_delayed  <= i_body_index;
      i_body_index_delayed1 <= i_body_index_delayed; 
    end
    
    // write new data into txram of compute engine (int16)     
    assign ena_txram0   = capture_new_x_in_txram;
    assign ena_txram1   = capture_new_x_in_txram;
    assign wea_txram0   = capture_new_x_in_txram;    
    assign wea_txram1   = capture_new_x_in_txram;
    assign dina_txram0  = { doutb_ram_x_new_int ,  doutb_ram_y_new_int };
    assign dina_txram1  = { doutb_ram_z_new_int ,  16'b0 };    
    assign addra_txram0 = i_body_index_delayed;
    assign addra_txram1 = i_body_index_delayed;
    
    // write new data into txrams of accelerator (fp27)
    assign addra_ram_x_new = i_body_index_delayed;
    assign dina_ram_x_new  = x_new_fp ; 
    assign enb_ram_x_new   = ~capture_new_x_in_txram ; // avoid write collision
    assign wea_ram_x_new   = capture_new_x_in_txram ; 
    assign ena_ram_x_new   = capture_new_x_in_txram ; 
    assign addrb_ram_x_new = ram_counter; 
    
    assign addra_ram_y_new = i_body_index_delayed;
    assign dina_ram_y_new  = y_new_fp ; 
    assign enb_ram_y_new   = ~capture_new_x_in_txram ; // avoid write collision
    assign ena_ram_y_new   = capture_new_x_in_txram ; 
    assign wea_ram_y_new   = capture_new_x_in_txram ; 
    assign addrb_ram_y_new = ram_counter; 
        
    assign addra_ram_z_new = i_body_index_delayed;
    assign dina_ram_z_new  = z_new_fp ; 
    assign enb_ram_z_new   = ~capture_new_x_in_txram ; // avoid write collision
    assign ena_ram_z_new   = capture_new_x_in_txram ; 
    assign wea_ram_z_new   = capture_new_x_in_txram ; 
    assign addrb_ram_z_new = ram_counter; 
    
              
    
   
    //----------------------------------------------------------------------------
    // here are all the definitions of the rams in this module 
    // 13 in total - these cannot be accessed outside this module
    // instance names denote function
    // ram_x,     ram_y,     ram_z,     ram_m : contain current x,y,z,m fp repr of input data
    // ram_x_new, ram_y_new, ram_z_new        : contain new x,y,z,m fp repr of output data
    // ram_vx,    ram_vy,    ram_vz           : contain velocities
    // ram_accx,  ram_accy,  ram_accz         : contain accelerations
    // just fix to this - port a for write and port b for read

 //  Xilinx Simple Dual Port Single Clock RAM -  ram to store x - fp
   xilinx_simple_dual_port_1_clock_ram #(
     .RAM_WIDTH(27),                       // Specify RAM data width
     .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
     .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
    // .INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
   ) ram_x (
     .addra(addra_ram_x),   // Write address bus, width determined from RAM_DEPTH
     .addrb(addrb_ram_x),   // Read address bus, width determined from RAM_DEPTH
     .dina(dina_ram_x),     // RAM input data, width determined from RAM_WIDTH
     .clka(clk),     // Clock
     .wea(wea_ram_x),       // Write enable
     .enb(enb_ram_x),         // Read Enable, for additional power savings, disable when not in use
     .rstb(rst),     // Output reset (does not affect memory contents)
     .regceb(1), // Output register enable
     .doutb(doutb_ram_x)    // RAM output data, width determined from RAM_WIDTH
   );   

 //  Xilinx Simple Dual Port Single Clock RAM -  ram to store y - fp
   xilinx_simple_dual_port_1_clock_ram #(
     .RAM_WIDTH(27),                       // Specify RAM data width
     .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
     .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
    // .INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
   ) ram_y (
     .addra(addra_ram_y),   // Write address bus, width determined from RAM_DEPTH
     .addrb(addrb_ram_y),   // Read address bus, width determined from RAM_DEPTH
     .dina(dina_ram_y),     // RAM input data, width determined from RAM_WIDTH
     .clka(clk),     // Clock
     .wea(wea_ram_y),       // Write enable
     .enb(enb_ram_y),         // Read Enable, for additional power savings, disable when not in use
     .rstb(rst),     // Output reset (does not affect memory contents)
     .regceb(1), // Output register enable
     .doutb(doutb_ram_y)    // RAM output data, width determined from RAM_WIDTH
   );   
 
  //  Xilinx Simple Dual Port Single Clock RAM -  ram to store z - fp
     xilinx_simple_dual_port_1_clock_ram #(
       .RAM_WIDTH(27),                       // Specify RAM data width
       .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
       .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
     //  .INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
     ) ram_z (
       .addra(addra_ram_z),   // Write address bus, width determined from RAM_DEPTH
       .addrb(addrb_ram_z),   // Read address bus, width determined from RAM_DEPTH
       .dina(dina_ram_z),     // RAM input data, width determined from RAM_WIDTH
       .clka(clk),     // Clock
       .wea(wea_ram_z),       // Write enable
       .enb(enb_ram_z),         // Read Enable, for additional power savings, disable when not in use
       .rstb(rst),     // Output reset (does not affect memory contents)
       .regceb(1), // Output register enable
       .doutb(doutb_ram_z)    // RAM output data, width determined from RAM_WIDTH
     );        
      
 //  Xilinx Simple Dual Port Single Clock RAM -  ram to store mass - fp
   xilinx_simple_dual_port_1_clock_ram #(
     .RAM_WIDTH(27),                       // Specify RAM data width
     .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
     .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
     //.INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
   ) ram_m (
     .addra(addra_ram_m),   // Write address bus, width determined from RAM_DEPTH
     .addrb(addrb_ram_m),   // Read address bus, width determined from RAM_DEPTH
     .dina(dina_ram_m),     // RAM input data, width determined from RAM_WIDTH
     .clka(clk),     // Clock
     .wea(wea_ram_m),       // Write enable
     .enb(enb_ram_m),         // Read Enable, for additional power savings, disable when not in use
     .rstb(rst),     // Output reset (does not affect memory contents)
     .regceb(1), // Output register enable
     .doutb(doutb_ram_m)    // RAM output data, width determined from RAM_WIDTH
   );     
   
   

   
//  Xilinx Simple Dual Port Single Clock RAM - ram to store new x - fp
 xilinx_simple_dual_port_1_clock_ram #(
   .RAM_WIDTH(27),                       // Specify RAM data width
   .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
   .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
  // .INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
 ) ram_x_new (
   .addra(addra_ram_x_new),   // Write address bus, width determined from RAM_DEPTH
   .addrb(addrb_ram_x_new),   // Read address bus, width determined from RAM_DEPTH
   .dina(dina_ram_x_new),     // RAM input data, width determined from RAM_WIDTH
   .clka(clk),     // Clock
   .wea(wea_ram_x_new),       // Write enable
   .enb(enb_ram_x_new),         // Read Enable, for additional power savings, disable when not in use
   .rstb(rst),     // Output reset (does not affect memory contents)
   .regceb(1), // Output register enable
   .doutb(doutb_ram_x_new)    // RAM output data, width determined from RAM_WIDTH
 );  
       
//  Xilinx Simple Dual Port Single Clock RAM - ram to store new y - fp
 xilinx_simple_dual_port_1_clock_ram #(
   .RAM_WIDTH(27),                       // Specify RAM data width
   .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
   .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
   //.INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
 ) ram_y_new (
   .addra(addra_ram_y_new),   // Write address bus, width determined from RAM_DEPTH
   .addrb(addrb_ram_y_new),   // Read address bus, width determined from RAM_DEPTH
   .dina(dina_ram_y_new),     // RAM input data, width determined from RAM_WIDTH
   .clka(clk),     // Clock
   .wea(wea_ram_y_new),       // Write enable
   .enb(enb_ram_y_new),         // Read Enable, for additional power savings, disable when not in use
   .rstb(rst),     // Output reset (does not affect memory contents)
   .regceb(1), // Output register enable
   .doutb(doutb_ram_y_new)    // RAM output data, width determined from RAM_WIDTH
 ); 
   
//  Xilinx Simple Dual Port Single Clock RAM - z ram to store new z - fp
 xilinx_simple_dual_port_1_clock_ram #(
   .RAM_WIDTH(27),                       // Specify RAM data width
   .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
   .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
   //.INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
 ) ram_z_new (
   .addra(addra_ram_z_new),   // Write address bus, width determined from RAM_DEPTH
   .addrb(addrb_ram_z_new),   // Read address bus, width determined from RAM_DEPTH
   .dina(dina_ram_z_new),     // RAM input data, width determined from RAM_WIDTH
   .clka(clk),     // Clock
   .wea(wea_ram_z_new),       // Write enable
   .enb(enb_ram_z_new),         // Read Enable, for additional power savings, disable when not in use
   .rstb(rst),     // Output reset (does not affect memory contents)
   .regceb(1), // Output register enable
   .doutb(doutb_ram_z_new)    // RAM output data, width determined from RAM_WIDTH
 );    
      
    //  Xilinx Simple Dual Port Single Clock RAM - vx ram to store velocity in x direction - fp
    xilinx_simple_dual_port_1_clock_ram #(
    .RAM_WIDTH(27),                       // Specify RAM data width
    .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
    .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
    //.INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
    ) ram_vx (
    .addra(addra_ram_vx),   // Write address bus, width determined from RAM_DEPTH
    .addrb(addrb_ram_vx),   // Read address bus, width determined from RAM_DEPTH
    .dina(dina_ram_vx),     // RAM input data, width determined from RAM_WIDTH
    .clka(clk),     // Clock
    .wea(wea_ram_vx),       // Write enable
    .enb(enb_ram_vx),         // Read Enable, for additional power savings, disable when not in use
    .rstb(rst),     // Output reset (does not affect memory contents)
    .regceb(1), // Output register enable
    .doutb(doutb_ram_vx)    // RAM output data, width determined from RAM_WIDTH
    );

    //  Xilinx Simple Dual Port Single Clock RAM - vy ram to store velocity in y direction - fp
    xilinx_simple_dual_port_1_clock_ram #(
    .RAM_WIDTH(27),                       // Specify RAM data width
    .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
    .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
   // .INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
    ) ram_vy (
    .addra(addra_ram_vy),   // Write address bus, width determined from RAM_DEPTH
    .addrb(addrb_ram_vy),   // Read address bus, width determined from RAM_DEPTH
    .dina(dina_ram_vy),     // RAM input data, width determined from RAM_WIDTH
    .clka(clk),     // Clock
    .wea(wea_ram_vy),       // Write enable
    .enb(enb_ram_vy),         // Read Enable, for additional power savings, disable when not in use
    .rstb(rst),     // Output reset (does not affect memory contents)
    .regceb(1), // Output register enable
    .doutb(doutb_ram_vy)    // RAM output data, width determined from RAM_WIDTH
    );
    
    
    //  Xilinx Simple Dual Port Single Clock RAM - vz ram to store velocity in z direction - fp
    xilinx_simple_dual_port_1_clock_ram #(
     .RAM_WIDTH(27),                       // Specify RAM data width
     .RAM_DEPTH(`MAX_PARTICLES),                     // Specify RAM depth (number of entries)
     .RAM_PERFORMANCE("HIGH_PERFORMANCE") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY" 
    // .INIT_FILE("")                        // Specify name/location of RAM initialization file if using one (leave blank if not)
    ) ram_vz (
     .addra(addra_ram_vz),   // Write address bus, width determined from RAM_DEPTH
     .addrb(addrb_ram_vz),   // Read address bus, width determined from RAM_DEPTH
     .dina(dina_ram_vz),