From chirp equation to a parameterized FPGA architecture that generates complex I/Q waveforms by changing only bandwidth and pulse width.
Use HC-SR04 on Arduino with Processing
Build a "speed trap" that uses ML to identify vehicles, a radar sensor to measure speed, and a cellular module to report data to the cloud.
Use the OmniPreSense RADAR and an Arduino to read surrounding speeds and even make part of flux capacitor replica!
Step-by-step guide to build a custom PetaLinux image for the ADRV9009 + ZCU102 after modifying the HDL reference design by Analog Devices.
Radar is an object detection system. Easy to design and cost effective
A powerful DIY home security system that uses radar to detect intruders with military-grade precision, even in total darkness
Animated NWS radar images & weather data in an old analog meter case!
Using MicroPython and Home Assistant to seamlessly integrate a doppler radar sensor for motion and presence detection into your smarthome.
A radar built using Power-KI, Arduino and LIDAR-Lite sensor.
Make a simple and cool ultrasonic radar using Arduino, an HC-SR04 sensor and a SG90 servo motor.
A radar system operates on ultrasonic sensor and it is used to detect the position or movement of the objects.
Radar project using Arduino and ultra sonic sensor SR04.
A Radar that detects objects with the help of sound waves is going to be implemented. Radar screen will be created on a HDMI screen.
Arduino complete project
A presence detection system combining HLK-LD2450 radar with a web interface.
Using the distance sensor as radar, viewing on a mobile phone.
This project shows you how to make a radar using an ultrasonic sensor.
In this project, FPGA-based ultrasonic radar screen have been developed, tested and applied. Design is made up of general and basic parts.
Fully pipelined implementation of FFT with fixed-point arithmetic in Vitis HLS
Adding smartness in vehicle entry and exit system.
Build your sonar at home!
This tutorial shows how to generate FPGA IP cores using Vitis Model Composer, from modeling to deployment—step by step.
Implementation of fully pipelined DDS IP cores in Vitis HLS with truncated, dithered phase and Taylor serial output correction
