Team POLARCA: halukunal, omeruzunoglan

Published April 12, 2018 © CC BY

Design of a Test System for Polar Codes in FPGA

We design a flexible, remote-controlled test system for polar codes in FPGA.

AdvancedWork in progressOver 83 days3,124

Design of a Test System for Polar Codes in FPGA

Things used in this project

Hardware components

Digilent Arty A7-35T

After the all tests successfully completed, we run our project in that board.

Digilent Nexys 3

Has more LEDs and switches, ideal for testing.

Software apps and online services

MATLAB

UART serial communication with FPGA for remote controlling, BER Calculations,

Vivado

Writing and simulating VHDL codes for modern boards.

Xilinx ISE

Writing and simulating VHDL codes for Nexys family cards.

Tera Term

For easy UART testing.

Story

Introduction

Polar codes are a channel coding technology which is most probably used in near future's trend 5G networks. Communication links are susceptible to errors due to random noise, interference, etc. That errors corrupt the original message at the receiver. Channel coding basically employs a set of algorithmic operations on the original data stream at the transmitter, and another set of operations on the received data stream at the receiver to correct these errors. In this project, a test system for polar codes will be implemented on Arty Z7 FPGA card using VHDL. We want to make our system very flexible. Flexible means that users can change any varible like message bits count, coding rate, binary erasure channel error probabilty whenever they want. So that, we need to send commands to FPGA and receive outputs from FPGA. Due to less amount of leds, switches on Arty Z7 board we decided to use serial communications like UART. We implemented and tested UART receiver and transmitter. For commands, we decided to create own operating codes table. In UART, message bits counts are eight, so first 4 bits are operation and last 4 bits are relevant data for selected operation. You can see first version of operation codes in Fig1, that table will be improved during development time.

Fig1: Simplified own UART Operations table

Implementation

We successfully implemented Polar Encoder and tested. Polar encoding is XOR operation according to some rules. It can be done static XORs for static message lengths but due to our flexibility mission, we use G_Matrix method for encoding operation. Each 1 (one) in the G_Matrix shows XOR operation. You can see that G_Matrix for eight bits and relevant XOR scheme in Fig2.

Fig2: Polar encoder using G_matrix

And in Fig3, here is the simulation result of our Polar Encoder implementation. In our implementation G_Matrix calculated from scratch according to 8 bits. We checked the encoded data Erdal Arıkan who is the inventor of the Polar Codes and it is true.

Fig3: Polar encoder simulation result

We used Nexus 3 for testing UART because it has 8 leds and switches. You can see UART receiver in Video 1 also UART transmitter in Video 2.

Video 1: UART Receiver

Video 2: UART Transmitter

To sum up, we implemented UART receiver, transmitter and Polar Encoder. We not implement UART operation codes because we focus on the Polar Decoder and most probably we will finish Polar Decoder in ten days. After the completion of FPGA parts we start the benchmark runs using operation commands and receive results of the benchmark runs. As the outcome of the project, we will create bit error rate(BER) graphs using received results from FPGA and we will see how close polar codes proposed for todays popular technologies like 5G networks will achieve a bit rate performance of Shannon’s theoretical limit. In video 3, you can watch short presentation about our project.

Video 3: Presentation

Thanks for reading so far.

library IEEE;
use IEEE.std_logic_1164.ALL;

entity main is
port(
		clk: in std_logic;
		reset,UART_RX,UART_TX_ENABLE: in bit;
		ledout: out bit_vector (7 downto 0);
		UART_LAST_TX: in bit_vector (7 downto 0);
		UART_TX: out bit
		);
end entity;

architecture logic_flow of main is
	type UART_STATES is (IDLE,TX_START,BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7,STOP);
	signal UART_STATE: UART_STATES := IDLE;
	type UART_MODES is (RX,TX,IDLE);
	signal UART_MODE: UART_MODES := IDLE;
	signal UART_CLK: std_logic;
   signal UART_CLK_COUNTER: natural range 0 to 5208:=0;
	signal UART_LAST_RX: bit_vector (7 downto 0);
begin

	process (reset, clk) begin
        if (reset = '1') then
            UART_CLK <= '0';
            UART_CLK_COUNTER <= 0;
        elsif rising_edge(clk) then
            if(UART_CLK_COUNTER = 5208) then
                UART_CLK <= NOT(UART_CLK);
                UART_CLK_COUNTER <= 0;
            else
                UART_CLK_COUNTER <= UART_CLK_COUNTER + 1;
            end if;
        end if;
    end process;
	
	
	 
	process(UART_CLK)
	begin
		
		if( reset='1') then
		ledout <= "00000000";
		UART_STATE <= IDLE;
		UART_TX <= '1';
		UART_MODE <= IDLE;
		elsif( falling_edge(UART_CLK) ) then
			case UART_STATE is
				when IDLE =>
					UART_MODE <= IDLE;
					if (UART_RX='0') then
						UART_MODE <= RX;
						UART_STATE <= BIT0;
					elsif (UART_TX_ENABLE='1') then
						UART_MODE <= TX;
						UART_STATE <= TX_START;
					end if;
				when TX_START =>
					if(UART_MODE=TX) then
						UART_TX <= '0';
					end if;
					UART_STATE <= BIT0;
				when BIT0 =>
					if(UART_MODE=RX) then UART_LAST_RX(0) <= UART_RX;
					else UART_TX <= UART_LAST_TX(0); end if;
					UART_STATE <= BIT1;
				when BIT1 =>
					if(UART_MODE=RX) then UART_LAST_RX(1) <= UART_RX;
					else UART_TX <= UART_LAST_TX(1); end if;
					UART_STATE <= BIT2;
				when BIT2 =>
					if(UART_MODE=RX) then UART_LAST_RX(2) <= UART_RX;
					else UART_TX <= UART_LAST_TX(2); end if;
					UART_STATE <= BIT3;
				when BIT3 =>
					if(UART_MODE=RX) then UART_LAST_RX(3) <= UART_RX;
					else UART_TX <= UART_LAST_TX(3); end if;
					UART_STATE <= BIT4;
				when BIT4 =>
					if(UART_MODE=RX) then UART_LAST_RX(4) <= UART_RX;
					else UART_TX <= UART_LAST_TX(4); end if;
					UART_STATE <= BIT5;
				when BIT5 =>
					if(UART_MODE=RX) then UART_LAST_RX(5) <= UART_RX;
					else UART_TX <= UART_LAST_TX(5); end if;
					UART_STATE <= BIT6;
				when BIT6 =>
					if(UART_MODE=RX) then UART_LAST_RX(6) <= UART_RX;
					else UART_TX <= UART_LAST_TX(6); end if;
					UART_STATE <= BIT7;
				when BIT7 =>
					if(UART_MODE=RX) then UART_LAST_RX(7) <= UART_RX;
					else UART_TX <= UART_LAST_TX(7); end if;
					UART_STATE <= STOP;
				when STOP =>
					if(UART_MODE=RX) then
						if (UART_RX='1') then
							UART_STATE <= IDLE;
							ledout <= UART_LAST_RX;
						else
							UART_STATE <= BIT0;
						end if;
					else
						UART_TX <= '1';
						UART_STATE <= IDLE;
					end if;
			end case;
		end if;
	end process;
	
	
end;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity polar_encoder is
generic(

	TOTAL_BITS:NATURAL:=8;
	TOTAL_BITS_LOG2:NATURAL:=3
	
);
port(clk:in std_logic;
y0:out bit_vector(1 to TOTAL_BITS);
y1:out bit_vector(1 to TOTAL_BITS);
y2:out bit_vector(1 to TOTAL_BITS);
y3:out bit_vector(1 to TOTAL_BITS);
y4:out bit_vector(1 to TOTAL_BITS);
y5:out bit_vector(1 to TOTAL_BITS);
y6:out bit_vector(1 to TOTAL_BITS);
y7:out bit_vector(1 to TOTAL_BITS);
encoded:out bit_vector(1 to TOTAL_BITS)
);
end entity;

architecture logic_flow of polar_encoder is
	type bit_vector_2d is array(1 to TOTAL_BITS) of bit_vector(1 to TOTAL_BITS);
	signal G_MATRIX : bit_vector_2d;
	signal generate_G_MATRIX: std_logic;
	signal generated_G_MATRIX: std_logic;
	signal ZERO_ROW:bit_vector(1 to TOTAL_BITS) := (others => '0');
	signal to_be_encoded: bit_vector(1 to TOTAL_BITS);
	
	----------------------
	function POLAR_ENCODE( MESSAGE : in bit_vector; G_MATRIX : in bit_vector_2d )
	return bit_vector is
		variable ENCODED : bit_vector(1 to TOTAL_BITS);
		variable XOR_temp : bit := '0';
	begin

		for I in 1 to TOTAL_BITS loop
			XOR_temp := '0';
			for J in 1 to TOTAL_BITS loop
				if( G_MATRIX(J)(I) = '1' ) then
					XOR_temp := XOR_temp XOR MESSAGE(J);
				end if;
			end loop;
			ENCODED(I) := XOR_temp;
		end loop;
		
		return ENCODED;
		
	end function POLAR_ENCODE;
	------------------------
  
begin

	generate_G_MATRIX <= '1';
	
	y0 <= G_MATRIX(1);
	y1 <= G_MATRIX(2);
	y2 <= G_MATRIX(3);
	y3 <= G_MATRIX(4);
	y4 <= G_MATRIX(5);
	y5 <= G_MATRIX(6);
	y6 <= G_MATRIX(7);
	y7 <= G_MATRIX(8);	
	
	G_MATRIX_GENERATOR: process(generate_G_MATRIX)
		variable current_dimension: positive:=2;
		variable next_g_matrix,current_g_matrix: bit_vector_2d;
	begin
		if(current_dimension=2) then
			--current_g_matrix:=(others => ZERO_ROW);
			current_g_matrix(1)(1 to 2) := "10";
			current_g_matrix(2)(1 to 2) := "11";
			for I in 1 to TOTAL_BITS_LOG2-1 loop
				next_g_matrix:=(others => ZERO_ROW);
				for J in 1 to current_dimension loop
					for K in 1 to current_dimension loop
						next_g_matrix(K)(2*J-1):= current_g_matrix(K)(J);
						next_g_matrix(K+current_dimension)(2*J-1):= current_g_matrix(K)(J);
						next_g_matrix(K+current_dimension)(2*J):= current_g_matrix(K)(J);
					end loop;
				end loop;
				current_g_matrix := next_g_matrix;
				current_dimension:=current_dimension*2;
			end loop;
			G_MATRIX<=next_g_matrix;
		end if;
	end process;
	
	to_be_encoded <= "00010101";
	encoded <= POLAR_ENCODE(to_be_encoded,G_MATRIX);


end architecture;

%% uart connect
s = serial('COM6');
set(s,'BaudRate',9600);
fopen(s);

%% UART receiver loop
i = 0;
while i<10000

    receive_ASCI = fscanf(s,'%c',1);
    received_binary = dec2bin(receive_ASCI);
    received_binary_vector = received_binary-'0';
    length_of_binary = length(received_binary_vector);
    if(length_of_binary<8)
        received_binary_vector = [zeros(1,8-length_of_binary) received_binary_vector];
    end
    received_binary_vector
    i=i+1;
    
end


%% clear
fclose(s);delete(s);clear s

Credits

halukunal

1 project • 2 followers

omeruzunoglan

1 project • 3 followers

Design of a Test System for Polar Codes in FPGA

Things used in this project

Hardware components

Software apps and online services

Story

Introduction

Implementation

Code

UART receiver and transmitter

Polar Encoder

UART Receiver Matlab

UART Transmitter MATLAB

Credits

halukunal

omeruzunoglan

Comments

Embed the widget on your own site

Design of a Test System for Polar Codes in FPGA

Design of a Test System for Polar Codes in FPGA

Things used in this project

Hardware components

Software apps and online services

Story

Introduction

Implementation

Code

UART receiver and transmitter

Polar Encoder

UART Receiver Matlab

UART Transmitter MATLAB

Credits

halukunal

omeruzunoglan

Comments

Related channels and tags