Pablo Trujillo
Published © CC BY

Creating a RISC-V system with an FPGA

In this project you will learn how to implement a RISC-V processor in a SmartFusion2 SoC.

IntermediateFull instructions provided2 hours3,238
Creating a RISC-V system with an FPGA

Things used in this project

Hardware components

Microchip Hello FPGA Kit
×1

Software apps and online services

Microchip Libero SoC 2021.2

Story

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Schematics

Mi-V Handbook

Hello FPGA Kit Schematics

Code

hw_platform.h

C Header File
hardware addresses for Mi-V processos
#ifndef HW_PLATFORM_H
#define HW_PLATFORM_H
 
/***************************************************************************//**
* Soft-processor clock definition
* This is the only clock brought over from the Mi-V Soft processor Libero design.
*/
#define SYS_CLK_FREQ                    25000000UL
 
/***************************************************************************//**
* Non-memory Peripheral base addresses
* Format of define is:
* <corename>_<instance>_BASE_ADDR
*/
#define COREGPIO_BASE_ADDR              0x70000000UL
#define COREPWM_BASE_ADDR               0x70001000UL

linker.cmd

C/C++
Linker file modifications for run program from eNVM
MEMORY
{
    envm (rx) : ORIGIN = 0x60000000, LENGTH = 240k
    ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
}
 
RAM_START_ADDRESS   = 0x20000000;       /* Must be the same value MEMORY region ram ORIGIN above. */
RAM_SIZE            = 64k;              /* Must be the same value MEMORY region ram LENGTH above. */
STACK_SIZE          = 2k;               /* needs to be calculated for your application */             
HEAP_SIZE           = 2k;               /* needs to be calculated for your application */

Credits

Pablo Trujillo

Pablo Trujillo

11 projects • 57 followers
FPGA designer for power electronics equipment. DSP and Power Electronics Control design specialist.

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