Published September 27, 2020

Digital clock (time watch) using FPGA

Digital clock (time) on 4 single 7 segment common anode display implemented hardware on Xilinx Spartan 6 FPGA.

IntermediateFull instructions provided1 hour2,861

Things used in this project

Hardware components

MINI_SP6-SPARTAN 6 FPGA DEVELOPMENT BOARD

common anode 7 segment display

minimum 4 display (for HH:MM). 6 displays can also be used for HH:MM:SS format.

Male/Female Jumper Wires

Breadboard (generic)

Software apps and online services

AMD Xilinx Software Development Kit

Xilinx ISE 14.07 (webpack edition).

Story

Digital clock (time watch) on 4 single 7 segment common anode display implemented hardware on Xilinx Spartan 6 FPGA. Use.ucf (implementation constrains) file to assign user IO ports of FPGA to Inputs & Outputs of.vhd (VHDL) file.

Code

Credits

Ninad Waingankar

12 projects • 21 followers

Robotics Embedded Systems Microcontrollers VLSI Designer FPGA Designer IOT