Vidbo: Graphical HDL Simulation Over Web Sockets
A neat open source project, Vidbo is a web server that facilitates graphical interface HDL simulations for FPGA development.
Most FPGA developers/engineers will agree that one of the headaches of designing is getting a good simulation set up to prove in the HDL design's functionality. Pretty much all of the IDEs for the FPGA chips out there (Vivado, Libero, etc.) have built-in simulators, but they don't always provide an intuitive view of what's going on. Olof Kindgren saw this gap in the market and addressed it with his latest open source project, Vidbo.
Vidbo, short for virtual board, is a web server with a graphical interface with a protocol created to communicate with a simulated FPGA development board or chip via web sockets.
While Vidbo can utilized for many different functions in simulation, initial prove-in of the software simply exposes I/O of an FPGA development board with a web browser GUI to control it.
Vidbo is the marriage of two previous projects of virtual development boards for HDL design and Verilatio which was the first revision of the web socket communication protocol with the HDL simulator. Each component of the virtual FPGA board or chip in the web browser GUI consists of three main components: the frontend HDL module, backend software library, and a transport layer between the frontend/backend.
The example project in the main Vidbo repository simulates a Nexys A7 board from Digilent with Verilog and C++ that implements the backend functionality of each component and HTML/SVG that comprises the front end web browser GUI.
The messages between the frontend and backend are JSON-encoded. Messages going from the simulator to the client contain timestamps indicating the current time of the simulation along with any of the output results of the simulation (e.g. LED was turned on, UART message was received, etc.).
Messages from the client to the simulator do not contain timestamps, they are the stimulus/inputs to the simulator (ie - turn the LED on, send "hello" over the UART, etc). The only catch is that the JSON struct does not guarantee any sort of order of operations so trying to send multiple commands to one peripheral of the virtual FPGA board in one message will result in undefined behavior.
This is a super impressive project, and is something that can be very handy for FPGA developers both hobbyist and professional alike. Vidbo still has a long list of TODOs marked in its repo as it is still in an early revision state, but is definitely one to keep an eye on!