ULX3S Is a Robust Open Source Lattice FPGA Development Board

A first impression of the new open source FPGA development board from Radiona, the ULX3S.

As FPGA development boards are catching up with microcontroller development boards in terms of popularity and demand, we are seeing an influx of new, feature-packed options pop up on crowdsourcing sites. Last week, the open hardware FPGA dev board ULX3S hit Crowd Supply's website ready for funding. In just four short days, the project has exceeded its modest $15,000 goal and is currently sitting around $17,000. After taking a look at the specifications of the ULX3S, it's not hard to see how Radiona hit their pledge goal in a short amount of time.

At the heart of the ULX3S is the Lattice ECP5 FPGA family. Lattice Semiconductor chips are a favorite for these maker-type FPGA dev boards due to their lower per-part cost, smaller footprint for compact layouts, and power efficiency. The TinyFPGA, Fomu, iCEBreaker FPGA, and OrangeCrab — which is currently funding as well on Hackster Launch — all host an FPGA chip from the Lattice lineup. The ULX3S is available in four different variations with pricing starting at $99 for the 12k LUT Lattice ECP5 (LFE5U-12F-6BG381C) FPGA and topping out at $155 for the 84k LUT Lattice ECP5 (LFE5U-85F-6BG381C) FPGA (if you scroll to the bottom of the page, there are still a couple of early bird deals left on this top level model for $135).

One of the biggest judgment points I have on any development board (microcontroller or FPGA) is its toolchain. Some boards have great hardware specifications, but their respective toolchain and IDE is just too much of a pain to install/use/obtain. The ULX3S has an open source toolchain utilizing the APIO IDE, based on Atom,Apio and Platformio-ide, specifically for developing hardware for the iCE40 Lattice FPGAs family to verify, synthesize, simulate and upload Verilog designs to the board. APIO is the development ecosystem for the ULX3S that brings together the Yosis synthesis tool, Lattice place and route tools, and tools for listing the USB devices and retrieving information from the FTDI chips.

Since the ULX3S's JTAG is routed through an FTDI to one of the USB ports, it's even possible to treat ULX3S as the Hulk of Arduinos and program it using the Arduino IDE. Once configured, over-the-air Wi-Fi flashes are also possible. An SD card can also be loaded with multiple bitstreams to switch between using the OLED and buttons as a sort of UI.

One of my favorite features that I feel makes the ULX3S really stand out in comparison to other FPGA dev boards on the market is its battery backed up RTC. This means that the board can fully power down and wait to be trigged by some sort of event to be powered up again while only drawing 5uA at 5V while in this sleep mode.

There is an ESP32 on the ULX3S that can be programmed to run independently or in conjunction with the FPGA. For those of you that aren't familiar, the ESP32 is a Wi-Fi and Bluetooth solution in a single package that is an ideal choice for keeping the communication overhead off your main processor since it is a standalone chip and simply uses a serial interface to work with an external processor. The ESP32 be be programmed natively using C/C++ with the Arduino IDE, the Visual Micro extension for Visual Studio, or the Espressif IDF commandline toolchain. It can also be configured for use with MicroPython, Espruino, the JavaScript SDK, NodeMCU, LUA, mruby, .Net C# nanoFramework, etc. This is make the ULX3S an ideal choice for IoT projects.

As an SDR enthusiast, the onboard antenna, 1MS/s ADC, DAC, SRAM, and 25 MHz oscillator are very appealing as it makes the ULX3S an all in one solution for basic SDR designs. Although I am curious about this onboard 433MHz antenna, I was able to find it called out on the schematic but with no corresponding part. It must be laid out as a patch antenna on the PCB directly connected to the Lattice FPGA chip (bonus cool points).

The ULX3S's full specification list from Radiona:

  • FPGA: Lattice ECP5
    LFE5U-85F-6BG381C (84 K LUT)
    LFE5U-45F-6BG381C (44 K LUT)
    LFE5U-12F-6BG381C (12 K LUT)
  • USB: FTDI FT231XS (500 kbit JTAG and 3 Mbit USB-serial)
  • GPIO: 56 pins (28 differential pairs), PMOD-friendly with power out 3.3 V at 1 A or 2.5 V at 1.5 A
  • RAM: 32 MB SDRAM 166 MHz
  • Flash: 4-16 MB Quad-SPI Flash for FPGA config and user data storage
  • Mass Storage: Micro-SD slot
  • LEDs: 11 (8 user LEDs, 2 USB LEDs, 1 Wi-Fi LED)
  • Buttons: 7 (4 direction, 2 fire, 1 power button)
  • Audio: 3.5 mm jack with 4 contacts (analog stereo + digital audio or composite video)
  • Video: Digital video (GPDI General-Purpose Differential Interface) with 3.3 V to 5 V I²C bidirectional level shifter
  • Display: Placeholder for 0.96" SPI COLOR OLED SSD1331
  • Wi-Fi / Bluetooth: ESP32-WROOM-32 supports a standalone JTAG web interface over Wi-Fi
  • Antenna: 27, 88-108, 144, 433 MHz FM/ASK onboard
  • ADC: 8 channels, 12 bit, 1 MS a/s MAX11125
  • Power: 3 Switching voltage regulators: 1.1 V, 2.5 V, and 3.3 V
  • Clock: 25 MHz onboard, external differential clock input
  • Low-Power Sleep: 5 µA at 5 V standby, RTC MCP7940N clock wake-up, power button, 32768 Hz quartz with CR1225 battery backup

This is a really awesome dev board options that a newer FPGA developer can definitely grow into, and more experienced developers can really do some amazing things with.

Check out this GitHub for the ULX3S PCB files and great compilation of example projects.

If you're interested in getting an ULX3S for yourself, head over to their campaign page.

They are transparent with the fact they are testing out manufacturing and distribution plans/choice with this first crowd funded batch, but they noted their backup plans in the event part of that supply chain goes down. However, with the unsure times that the COVID-19 virus has brought us into, I really hope to see this project succeed and make it to market.

Whitney Knitter
All thoughts/opinions are my own and do not reflect those of any company/entity I currently/previously associate with.
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