It's safe to say that Australia-based Davill knows his stuff, so it's with keen anticipation that we tear into the latest thunder from down under: the OrangeCrab.
Some might say that these project names are getting a bit weirder, but hey, that's how a memorable name works. And well, it is orange, but thankfully, none too crabby, nor at all shabby!
This board brings the might of the power we normally see on much larger FPGA dev boards to the familiar Feather form factor that we all know and love.
- A Lattice Semiconductor ECP5-25F FPGA, with 24K LUT elements, 1008Kb block RAM, 194Kb distributed RAM.
- This is the smaller sibling of the part found on the 2019 HaD Super Conference badge, and the same family supported by the Radiona ULX3S.
An FPGA such as this one can churn through bits, so we are pleased to see a multitude of memories to cover a variety of applications:
- 1 Gbit DDR3 memory (organized as 64M x 16 bit)
- 128Mbit QSPI flash (with 4Mbit used for bootloader) is free to store the FPGA bitstream, firmware for the SoC (more on that later) or other uses.
- a μSD card slot rounds off the storage options, providing an ever increasing maximum storage potential, somewhere around 512GB at the moment?
An open source bootloader is provided to allow you to connect over the FPGA's native USB interface to upload code and access the memories over MSD, but there's also a standard 2x5, 1.27mm header to give you JTAG straight in. Great for those of you looking to develop applications on the USB layer.
This is a skilfully designed board. From the csfBGA285 FPGA package, to the six-layer stack needed to support all the signals present, to the sheer number of tiny passive RLC parts, there's a lot going on. Just look at that board stack!
Once again, we should note that what we see from Davill is not only designed by him, but also hand placed and assembled. Looking at the output from the InteractiveHtmlBom plug-in for PCBNew, we can get a nice clear view of the component placement. Even with everything going on up on the top layer, there are still passives galore on the bottom face of the board.
Parts on this scale are a bit less likely to drop off the board during the second paste and reflow operation that would have to occur with hobbyist setups. And while it might be larger than its cousin Fomu, a board with this many tiny parts to assemble is no small feat. It's very impressive that Davill has been building these boards with his own hands!
Anyone who has designed in any sort of high speed interface can appreciate the difficulties faced by the constraints imposed when routing the PCB layout.
Let's consider the DDR3 RAM interface found on the OrangeCrab board. Below, is a screenshot of the part, with the signals needed to interface with the memory shown, in KiCad's EESchema.
There are a lot of nets needed to connect all the signals of the data bus, address bus and control lines to the FPGA I/O. Routing is further compounded by the need to length match grouped traces, in order to meet the DDR3 bus peeds, which can top out at a throughput of 1866MT/s (megatransfers per second) this part, a Clock cycle time of somewhere around 1.07uS.
As the MT41K64M1`6TW is DDR3 (Double Data Rate) memory, that's a peak clock rate of somewhere around 1066MHz, which means even carelessly laid stubs for termination resistance and such can criple the transfer rate. These speeds can therefore still dictate some pretty tight tolerances when trying to length match such traces.
Practically, getting multiple PCB traces matched to within fractions of a mm, in any number, poses some challenges. Pad placement on packaging can only go so far in trying to optimize trace routing, so how do designers "pick up the slack," and get the track lengths more evenly matched across the group?
KiCad's PCBNew uses an XML based board file format, enabling such neat tricks as this handy Python Script that monitors the board file directly. When closed, it pulls the routed net lengths from the XML data into the required groups and calculates the difference across that group.
With this information now to hand, Davill can then use a process known as meandering, where the track turns back and forth along its direction of travel, adding the extra length needed.
It's usually easier to add extra to bring the group average up to one of the group outliers than it is to start shaving length off already routed tracks!
With the Python Console capabilities found within PCBNew, I don't imagine it will be too long before this sort of functionality is pulled into the program, but for now, it's still a bit of a manual process to iterate through multiple passes that would likely be needed by all but the most seasoned layout guru.
From all the periphery we've seen so far, this seems to be a pretty digitally focused board. However, all is not forgotten in the name of our old friend analog. The Feather standard has been adhered to as fully as possible, in even providing a full compliment of six analog inputs.
Given the ECP5 only has one SAR ADC input, there's obviously something else going on to map that to the six physical input pins.
A 74HC4067 16-Channel Analog Multiplexer/Demultiplexer steps up to the challenge, and with six inputs routed to the external pins of the board, there are a few left over to pull in some useful measurements such as the various voltage rails and the voltage present on the battery input header.
Last week, we wrote on the Open Hardware Summit badge and spoke of how it is a great example of open source hardware design. This takes it to the next level of embrace, with not only the board being designed with open source EDA tools, but the gate-level hardware design and synthesis that flows through a fully open source toolchain.
The OrangeCrab wears its OSHW badge with pride, taking place at number six on Australia's hardware list (we can't help but wonder who the other boards are designed by...), it has been created using KiCad, our favourite open source EDA suite.
Fully compatible with the open source FPGA toolchain and flow, with synthesis being handled by Yosys, Place and Route being taken care of by Nextpnr, and Trellis providing the documentation and utilities.
Davill has ideas of porting over CircuitPython to this board, which is certainly more than capable of hosting the interpreter. While not currently implemented, the user is still free to target the FPGA itself with "gateware" — synthesized HDL.
For those more familiar with an SoC-level development platform, the ECP5 is capable of running a RISC-V softcore, with a huge amount of flexible ycapabilit being offered through the LiteX project.
And like it's bigger brother, the HaD badge, also based on the ECP5 family, the specs of the OrangeCrab mean it can of course boot up Linux!
Even the bodge wire jobs we see turning up with Davills work are pretty nifty. Check out this lash-up below. What might look at first like Mini USB connector inverted over the usual placement of the battery JST connector, on closer inspection, has a few too many pins for USB...
Taking a second glance, we recognize it as instead a MicroHDMI connector, with signals being AC coupled to the ECP5 I/O through tiny SMD caps soldered to the right hand side PTH header. Throw those parts on a simple FeatherWing, and for a few dollars, you have a working HDMI 1080p25 output from this beast.
With all the peripherals found on the OrangeCrab, it's a solid contender for some real world applications, and would serve well as an addition to any hobbyist of FPGA enthusiast hardware collection.
If you aren't quite up to the challenge of a double sided assembly of BGA packages and 0201 passives however, you're in luck. Hackster and GroupGets are excited to announce a new platform to help get fresh, innovative hardware products such as the OrangeCrab into production.
Hackster Launch aims to close the loop on the critical early steps that can make or break a crowdfunding campaign. By offering an established platform for backers to effectively communicate their feedback to the designers, adjustments can be made early on, and designs verified and tuned to ensure the best possible product for both the developer and the end user.
You can check out the OrangeCrab there, where you can pledge to support this project, and be one the recipient of one of the first production batch runs of the board.