Given their power and flexibility, FPGAs have become a staple in the maker space. Unfortunately their flexibility comes at the cost of an elevated complexity level, making something even as simple as a blinking LED a challenge to get setup for someone who is either new to FPGAs as a whole or new to that particular FPGA chipset.
As an answer to this problem, FPGA developer Dave, created Nysa. Nysa is a tool in the form of a development platform that enables a user to simply drop custom IP cores and modules into a bus in the FPGA. This bus handles the communication protocols for passing data back and forth to a host PC via a simple Python API.
Nysa started when Dave found an LCD screen that he wanted to interface with his Diligent Nexys 2 board. He quickly found that the simple task of adding a new device to the FPGA's ecosystem wasn't so simple.
With the desire to have a tool akin to the Arduino IDE in its simplicity, Dave set out to make a graphical UI that made testing new hardware with an FPGA project more so a matter of downloading code and just tweaking it to fit in the design.
The Nysa software consists of three main components: the core builder, the image builder, and the host.
The core builder handles the generation of customs cores and IP blocks. It output Verilog projects with both the RTL as well as the build tools to verify the design, simulate it, and view waveforms. Once the design is complete, it is passed to the image builder to be compiled into the final FPGA image.
The image builder also takes generated image and instantiates a block ROM within the FPGA that can be used with the Host Python API for design analysis. This Host API interacts with the image on the FPGA via read and write commands along with some helper functions.
Nysa is currently capable of supporting up to 6 peripherals without a user needing to write any HDL, but rather just dragging and dropping in the GUI interface. Nysa also supports SATA and DDR interfaces. Check out the project details here along with future updates.