MicroZed Chronicles: MicroZed (Zynq-7000) Vitis Platform Creation

How to create a Vitis acceleration platform for the MicroZed / Zynq-7000 family.

I have previously shown how to create a Vitis platform (P1,P2,P3 &P4), which can be used for acceleration targeting a Zynq MPSoC on a Ultra96 V2.

In this blog, I am going to show how we can create a Vitis acceleration platform for a Zynq-7000 on a MicroZed.

While the process is very similar, there are a few slight differences that I think justify having its own article.

Note: Before we start this make sure you have run all the Vitis, Vivado and XRT set up scripts.

The first thing we are going to do is create the directory structure. For this, we need a directory named microzed_pkg, under this create directories called pfm and vivado.

Under the pfm directory, create two further directories called wksp1 and boot.

mkdir microzed_pkg
cd microzed_pkg
mkdir pfm
cd pfm
mkdir wksp1
mkdir boot
cd ..

Under the Vivado directory, create a new Vivado project targeting the MicroZed 7020 board.

Name the project MicroZed — this will be the name of the PetaLinux project name and Vitis platform as well.

Within the Vivado project, create a new block diagram, add in a Zynq processing system, and run the block automation to configure it for the MicroZed.

Once the block automation has been completed, recustomize the Zynq PS and under the MIO configuration tab uncheck the Timer 0 option.

The next step is to add in a clocking wizard and configure the clocks as follows. CLK1 = 100MHz, CLK2 = 125 MHz, CLK3 = 150 MHz & CLK4 = 250 MHz.

Set the reset input to be active low.

We also need to be able to support interrupts from the fabric to the PS — on the Zynq recustomization tab, enable the PL-PS interrupts.

The next step is to add in four processor reset blocks, one for each of the clocks we have just defined.

With all the IP blocks added to the design, we are then ready to connect them using connection automation.

In the dialog box, pair each of the processor reset clocks with one of the clock wizard outputs. The reset comes from PS fclk0 reset.

Once this has been completed, the block diagram will look as below. The one last thing remaining is to connect the concat block and connect the locked signal from the clocking wizard locked output to the processor reset system DCM locked inputs.

We now need to make platform interfaces available for use in the XSA and Vitis. To do this, select the Platform Interfaces option from the Window tab and enable the view.

Within the platform interfaces, enable the M_AXI_GP0 & 1, S_AXI_HP0 to 3.

We also need to enable the four clocks on the clocking wizard, assign clock 0 to have an ID of 0 and be the default. Ensure all of the other clock IDs increment sequentially from 0.

In addition, we need to enable 8 of the IRQs on the concatenation IP block. With this completed, implement the design and generate the bitstream.

Once these have been defined using the TCL command window, enter the following commands to define the application as a embedded system.

We can then export the hardware platform as an XSA.

set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type "sd_card" [current_project]
write_hw_platform -include_bit ultra96_min.xsa
validate_hw_platform ./ultra96_min.xsa

SW Creation

We are now ready to create the SW operating system using PetaLinux. Under the microzed_pkg directory, create a new PetaLinux project called "microzed."

petalinux-create -t project --template zynq --name microzed
cd microzed
petalinux-config --get-hw-description=../vivado

Once this opens, the configuration dialog change the boot arguments from being auto generated to:

earlycon clk_ignore_unused root=/dev/ram rw

We need to update the kernel configuration settings as well for the following:

  • Device Drivers > Generic Driver Options > DMA Contiguous Memory Allocator > Size in Mega Bytes change the size from 16 to 256MB
  • Device Drivers -> Staging drivers -> Xilinx APF Accelerator driver
  • Device Drivers -> Staging drivers -> Xilinx APF Accelerator driver -> Xilinx APF DMA engines support

We also need to make some changes to the Yocto user later under <project>/project-spec/meta-user add in the following to the conf file.

CONFIG_xrt
CONFIG_xrt-dev
CONFIG_zocl
CONFIG_opencl-clhpp-dev
CONFIG_opencl-headers-dev
CONFIG_packagegroup-petalinux-opencv

We also need to make some changes to the device tree which is located at <project>/project-spec/meta-user/system-user.dsti.

&amba {
zyxclmm_drm {
compatible = “xlnx,zocl”;
status = “okay”;
};
};

Once these have been implemented, we can configure the rootfs to include the user packages we have just defined.

petalinux-config -c rootfs

Once this is completed, we can build the PetaLinux image using the command:

petalinux-build

Wait until the build completes and we can then create a sysroot, change directory into the <project>/images/linux/ directory, and run the command

petalinux-build --sdk

We can then install the sysroot within the pfm directory using the command, when prompted provide the full path to the pfm directory.

./sdk.sh

Once the sysroot is installed copy the files from the <project>/images/linux/ to the pfm/boot directory:

  • image.ub
  • zynqmp_fsbl.elf
  • u-boot.elf

Within the pfm directory, we need to create a linux.bif file

the_ROM_image:
{
[bootloader] <zynq_fsbl.elf>
<bitstream>
<u-boot.elf>
}

Platform Creation

From within the pfm directory, launch Vitis with the following command:

vitis -workspace wksp1

Once Vitis loads, select new platform project creation and enter the name MicroZed.

The design will be created from an XSA. Point Vitis to the location of the XSA we exported from Vivado and select a Linux OS.

Once the project creation is completed under the Linux domain, we need to provide the location of the BIF file and the location of the boot components, Linux image, and sysroot.

The boot components and Linux image are provided under the boot directory, while sysroot will be located under the pfm/sysroots directory.

We can then build the project. Once the project is built, we are then able to start a new application project.

You should see the MicroZed platform — which is available for both embedded and acceleration flows — select that platform, and create a project based on the vector addition example.

From within the Vitis environment, select a hardware build, and wait for he build to be completed. It took around 10 minutes on my machine for the system to be created.

If we want to see what hardware was implemented within our design we can open Vivado and observe the finished solution.

Using Xilinx->Vivado Integration->Open Vivado Project, this will prompt us to select the binary container we wish to examine.

Within Vivado, opening the block diagram will show the design as implemented within our solution.

We can then copy the files from under the SD card directory in Vitis to a SD card and boot our MicroZed.

To run the application on the MicroZed, we can use the commands:

cd /run/media/mmcblk0p1
export XILINX_XRT=/usr
./test.exe binary_container_1.xclbin

This will run on the target and should provide an indication of the test status.

Now we know exactly how to create acceleration platforms for the Zynq and Zynq MPSoC.

You can learn more about the Xilinx Runtime here:

https://xilinx.github.io/XRT/2019.2/html/platforms.html

See My FPGA / SoC Projects: Adam Taylor on Hackster.io

Get the Code: ATaylorCEngFIET (Adam Taylor)

Access the MicroZed Chronicles Archives with over 300 articles on the FPGA / Zynq / Zynq MpSoC updated weekly at MicroZed Chronicles.

Adam Taylor
Adam Taylor is an expert in design and development of embedded systems and FPGA’s for several end applications (Space, Defense, Automotive)
Related articles
Sponsored articles
Related articles