Last week, we looked at how we could create a virtual machine that would enable us to accelerate Vitis applications. This week, we are going to look at how we can create the hardware element of this Vitis platform.
To do this we will be using Vivado — the board I am going to target is the Ultra96 — and we will need the board files which can be obtained here.
Boot the VM that we created last week.
The first thing we are going to do is create the necessary folder structure, using a terminal. Enter the commands:
Once in the Vivado directory, we can start Vivado and create a new project — make sure we target the Ultra96 V2 board.
With the project open, the next step is to create the block diagram.
When the create block diagram dialog appears, leave the name as design_1 and click OK.
In the block diagram, we need to add the MPSoC processing system and configure it for the Ultra96 V2 by running the block automation.
Now that we have the processing system configured for a base Ultra96 V2 project, we can configure it how we need for an acceleration XSA by re customizing the MPSoC IP.
The first step is turn off the AXI HPM0 and HPM1 FPD interfaces.
With the MPSoC configured as we desire, the next step is to implement the clocking and reset structures.
Let's start with adding in a Clocking Wizard IP Block and re-configuring it to provide five outputs. Increasing in frequency from 100 MHz to 400 MHz make the fifth clock output 600MHz.
To ensure the reset on the clocking wizard is compatible with the MPSoC IP block reset, we need to set the clocking wizard reset to be active low.
To function correctly in the Vitis acceleration flow, each clock needs an associated reset. So now let's address this.
To add in a processor system reset IP, we need one of these for each of the clock outputs on the clocking wizard. Copy and paste this four times so we have a total of five in the block diagram.
At this stage our block diagram should look as below:
Run the connection automation and associate each processor reset block, slowest sync clock with one of the clocking wizard clocks.
Set each of the ext_reset_in signals to the pl_resetn0 output from the MPSoC.
Once the automation has completed, the final stage is to connect the dcm_locked inputs on the processor reset systems to the locked output on the clocking wizard.
Finally, add a Concat IP block and connect it to the PL-PS_IRQ input. Ensure there is only one input on the concat block.
Having completed the base platform, the next stage is to declare capabilities which will be made available or not to the V++ compiler.
To do this, first we need to enable the platform view — this is enabled by selecting:
Window -> Platform Interfaces
This will create a new Platform Interfaces window within the block diagram.
Click on the Enable Platform Interfaces, and you will see a list of the available interfaces under each of the elements in the design.
These can be enabled or disabled by right clicking on the interface. For the Ultra96 V2 MPSoC, ensure the interfaces below are enabled.
Select clk_out3 and in the options below set the ID to 0 and make it the default clock.
Finally, enable In0 to in7 on the Concat block.
We also need to set the design intent to show where we are intending to deploy the design enter the commands below in the TCL console.
set_property platform.design_intent.embedded true [current_project]
set_property platform.design_intent.server_managed false [current_project]
set_property platform.design_intent.external_host false [current_project]
set_property platform.design_intent.datacenter false [current_project]
set_property platform.default_output_type "sd_card" [current_project]
Save the project, validate the block diagram, and generate a HDL wrapper for the block diagram.
Once we have the HDL wrapper implement the bit stream.
Wait until the bitstream is available, then export and validate the XSA with the following TCL commands:
write_hw_platform -include_bit ultra96_min.xsa
Now that we have the hardware element of the platform created, we can start looking at the software element next.
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