Efabless' CLEAR Is a Fully Open Source ASIC with Embedded FPGA and RISC-V Core, Now on GroupGets
Designed to introduce people to the chipIgnite custom ASIC production platform, CLEAR is at once a functional dev board and a tech demo.
Chip design specialist Efabless has launched an open source FPGA chip dubbed CLEAR, built on its own chipIgnite platform and offering a completely open design — right down to its CPU core.
"CLEAR is an open source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC [Application Specific Integrated Circuit] design tools used to create it," Efabless explains of the project. "That's for you to create your own - yes that's right - ASIC."
CLEAR is built on Efabless' chipIgnite platform, itself an expansion of the open-hardware ASIC production offering it launched in partnership with Google and SkyWater a year ago. Where the Open MPW Shuttle Program required submissions to be properly-licensed open hardware and in return funded production of physical chips based on the Caravel ASIC platform, chipIgnite is open to all for a one-off $9,750 per project — a fraction of the typical cost for getting a chip design produced in silicon.
The idea behind CLEAR is to demonstrate just how easy it is to get started with ASIC design. "As part of the campaign we will show you everything we do including how to design your own ASIC with open source ASIC design software and how you can create a campaign just like this one for your own custom ASIC," Efabless explains. "All that without having to make a giant hole in your pocket for ASIC design and manufacturing."
Running through the GroupGets group-buying platform the CLEAR campaign includes the production of an embedded FPGA macro via the OpenFPGA generator framework, its integration into the Caravel platform, manufacturing of the resulting ASIC via chipIgnite, packaging the chips, mounting them on the carrier development board, testing them, and delivery of the hardware.
Each board will include a full open source ASIC featuring an 8x8 CLB embedded FPGA (eFPGA) alongside a VexRISCV-based RISC-V processor, 3kB of on-chip RAM split between 2kB of OpenRAM and 1kB of DFFRAM, execute-in-place support from external QSPI flash, and peripherals including SPI, UART, counters, timers, a logic analyzer, and 39 software-configurable general-purpose input/output (GPIO) pins.
The campaign is now live on GroupGets; pricing has been set at $74.99 plus shipping per board, with a target of 200 boards. The funding campaign is scheduled to end on March 28th, 2022, with hardware to be delivered in September if enough designs are booked onto the April manufacturing shuttle.