We now have professionally-produced panels of PCBs, for mere peanuts.
There are myriad microchips for not much more than a fast food meal that can run circles around the computers that took man to the moon.
And even FPGAs allow for makers to model digital systems out of real hardware, by doing little more than burning a bitstream.
In recent news, we've even touched on the likes of Sam Zeloof — a hardware maker in one of the truest senses — fabricating custom silicon chips in his garage.
Yeah, things seem pretty Star Trek right now, it's got to be said.
And, even if the homebrew garage fab lab is a bit beyond the reach and discipline of the average maker, there are new alternatives on the horizon that put that ability back into the realms of reality, much in the same way PCB Pool services do for the fabrication of two-eight layer boards for our own purposes.
So where do we go from here? Well, buckle up, because it's about to get pretty wild, thanks to the efforts of efabless, Google and SkyWater, who have teamed up to offer something called the Open MPW Shuttle Program.
What's on offer? The ability to create your own fully custom ICs quickly and easily, using pre-verified blocks of efabless IP dragged into your design as required
The MPW part of the tagline is a new acronym for us — but easy to grok once heard in full — Multi Project Wafer. Whereas a normal wafer fabrication process will see a single chip design laid out en masse over the mask set, the MPW aims to pool a number of project designs onto the same wafer!
With the MPW designs locked in, SkyWater go to work, and with a business model similar to that of OSH Park, pool designs together, before coating, doping and etching the designs present on that shuttle into real life ASICs — manufacturing, bonding and packaging 10 parts of each design, ready for integration by the end customer!
Complete custom ASICs, designed in a drag-and-drop web environment, with 10 copies produced on an industrial process, for free!
I can fire up my browser — right now, as I write this — navigate to the efabless portal, and spin up a complete ASIC design, all with a few keystrokes. This is the start of something really interesting and pretty mind-blowing when you think about it! Let's see where this is going!
What you see in the image above is the view of the first step of it all — selecting the Caravel-based user project on the efabless cloud-hosted workspace!
But perhaps we should cover some of the ground rules before jumping in...
Getting a custom chip fabricated has long been quite the investment, and certainly no short undertaking!
The NRE (non-recurring engineering) costs associated with even a simple ASIC will likely run into the 6 figure mark.
Not only does the design require skilled knowledge in the fundamental construction building blocks of a chip-level design, there is also core IP that usually bootstraps the design of the chip.
Even once the chip is designed — hopefully correctly! — there are the costs associated with the mask tooling, required by the photolithographic processes that will develop our silicon wafers into functional chips.
Indeed, this isn't an endeavor that has ever reasonably favored low volume production quantities, nor the wallets of you and I.
With the offer of free, pre-designed blocks of IP for makers to build from — and with additional tooling costs being sponsored by Google — the Open Shuttle Program is free to any open source design that can meet the programs requirements.
Which are? We'll take a look at the technical points enforced by the programs requiements below.
The project must be targeted on the currently-supported SkyWater Open PDK for the 130nm process.
The project must be fully open. The project must contain a GDSII layout, which must be reproducible from source contained in the project.
GDSII? Consider this file format something akin to the layer stack that we all know and love — the Gerber data for our PCBs — but instead for mapping out the metal oxide layers and interconnect wiring that will be etched into and formed upon the custom ASIC.
This seems a pretty sensible requirement — in such a way that many of us would cry foul of the open source terminology in a project that did not include board Gerbers!
Projects must use a common test harness and padframe based on the Caravel repo. The projects must be implemented within the user space of the layout and meet all requirements for the Caravel.
The padframe refers to the physical dimensions and locations of the bonding pads present around the outside of the chip.
A silicon chip needs to be housed within a package and carrier, with the legs of the carrier connected to these bonding pads with a process known as wire-bonding — seen below.
As such, with a fixed harness (the Caravel) and a fixed packaging process, the locations of these bond pads are defined and fixed across every design through the Open MPW Shuttle.
There's the Caravel again. The Caravel got a mention back at the start of the article — and no, we aren't talking about the 16th century sailing ship sailing the high seas — this is something else, designed to help ailing ICs!
Caravel is a block of pre-validated IP is a reference design block for the SkyWater process, and massively bootstraps the design process for any new chip — by providing a pre-made "host" onto which you can graft your "user project."
That's very, very handy!
Based around a PicoRV32 RISC-V core, with clock speeds in the region of ~50MHz, the Caravel provides a number of peripherals to the project area. Beyond power management and other core functions, the list includes
- 1 SPI flash controller
- 1 UART
- 1 SPI controller
- 2 counter-timers
- 1 dedicated GPIO channel
- 27 shared GPIO channels
- 8k word (32768 bytes x 8 bits) on-board SRAM
- All-digital frequency-locked loop clock multiplier 128bit logic analyzer.
The logic analyzer is a very interesting prospect — giving low-level, on-chip access to the various probe points defined — up to 128 of them.
Projects must successfully pass the Open MPW precheck tool, including LVS and DRC clean using the referenced versions of OpenLane flow.
This seems fair enough — with such a generous investment from Google in regard to covering the costs of chip manufacture, test and packaging, it makes good sense to ensure that the shuttles aren't just loaded up with "eh, let's see" approaches. The program wants to see as many success stories as possible, so the Open MPW precheck tool will aim to validate as much as possible in the new Caravel-based ASIC you've just designed!
Speaking of success stories... Well...
The OpenTDC design from Tristan Gingold is a time-to-digital converter with a precision of < 1ns, and provides a fine delay function of equal precision.
With obvious applications of laser ranging (including LIDAR and 3D mapping), other uses include time-of-flight measurements for observing particles generated by experiments in high-energy physics.
While not designed for practical deployment on any real blockchain, the SKY130 SHA3 Miner Caravel SOC is proof-of-work cryptominer demonstrator for a hypothetical blockchain hashing function that that is based on the SHA3-256 Hash.
With this design showing 12 of the 24 pipeline stages required for the full throughput, the need to split the miner implementation over two chips could overcome — with some careful, manual review of the some 300,000 auto routed cells and 1,000,000 interconnect traces!
Novelic, a design firm who look to specialize in the design of radar sensing systems, have created a Spectravel; a Caravel harness that implements a spectrometer ASIC, designed using the Chisel language.
Chisel itself is a new one to me, and looks — as far as I can see — to be a sort of contender to conventional VHDL / Verilog in as much a way as Python is a "contender" to C / C++, in that different programming paradigms provide different ways to approach problem solving.
With the high-level layout of their ASIC block features and interconnects defined in the schematic below, it's pretty mind boggling (for now, at least!) in how that translates to the large squiggly-looking auto placed mass of interconnected logic cells, generated by the efabless Place and route auto tooling!
With a whole suite of open source projects for Caravel-based designs currently available for you to review and dig into online, there's no better time than now to start familiarizing yourselves with with what we hope will soon become a more common place process.
While these three designs above focus on digital blocks, we can see Caravel-based ASIC designs within the efabless gallery that feature analog elements, such notable examples as this Amateur Radio Satellite Transceiver ASIC design from Thomas Parry, which is a strong contender for demonstrating what the Open MPW Shuttle program enables.
With a Fractional N-Phase Locked Loop block visible above, and the transceivers bandgap block visible below, these two parts alone look like a significant design effort — but seem to barely occupy the available die space!
In fact, you can count three of the bandgap blocks in amongst the empty space at the bottom right of the full die shot below, along with the single VCO, sat in the middle of the components along of the upper section of the user project area.
And while perhaps google might not keep shelling out the operation costs forever — this initial contribution will surely help direct the overall cost of ownership of such a Shuttle project into the realms of affordability by you and I alike!
For any one who might scoff at that, we suggest that you take full advantage of the program now while it's free!
Understandably, the process is still somewhat more involved than say, the likes of ordering a panel of PCBs. But, do remember that this is an full ASIC that's being created here — and with that in mind, the process being offered by the Open MPW program is something that is already far more user accessible than we'd ever imagined would be possible.
Read more on the fascinating Open MPW Shuttle here!