Dangerous Prototypes Upgrades the Bus Pirate with iCE40 FPGA Power, Creates the Bus Pirate Ultra

Bus Pirate Ultra design offers considerably more flexibility and power than the project's still-popular microcontroller-based predecessors.

Gareth Halfacree
4 years agoFPGAs
The Bus Pirate Ultra is a major upgrade from its predecessors. (📷: Dangerous Prototypes)

Dangerous Prototypes' Ian Lesnet has begun a pre-emptive retrospective into his company's latest board design: the Bus Pirate Ultra, which upgrades the original Bus Pirate with an onboard Lattice Semiconductor iCE40 field-programmable gate array (FPGA).

The original Bus Pirate design, still available from production partner Seeed Studio, was designed as a universal bus interface connecting a computer's USB ports to any one of a range of serial bus types - from 1-Wire and SPI through to MIDI and PC keyboard connections - without any programming on the user's part. Traffic sniffers, frequency measurement, pulse generation, and a pulse-width modulator aided with identification of unknown target devices while a low-speed logic analyser proved handy in a pinch.

The Bus Pirate Ultra takes the core concept, complete with the same interface, but offers considerably more potential thanks to the integration of an iCE40 FPGA. "Previous Bus Pirates relied on the hardware peripherals available in a microcontroller, which vary in features and have the occasional bug," Lesnet explains. "With an FPGA we can implement practically any peripheral with all the fixes and hacks we want! SPI, I2C, UART, CAN? Yes! Master or slave? Both! Complex frequency generator? Yup! Full featured JTAG debugger? Don’t see why not!"

"A big STM32F103ZE microcontroller connects to an iCE40HX4K FPGA through a 16-bit bus that can move a ton of data. The fully buffered interface is capable of high-speed signalling from 1.2 volt to 5 volts. 128Mbit of RAM powers a logic analyser with a potential maximum speed over 200MSPS. A 32Mbit flash chip stores up to 30 bitstreams with different features that can be loaded into the FPGA by the microcontroller."

Lesnet's blog post goes into considerable detail about the thinking behind the Bus Pirate Ultra design, which has its origins in an aborted design for a Bus Pirate upgrade based on the STMicroelectronics STM32 microcontroller. Though the hardware has yet to be released for sale, Lesnet's retrospective discusses the v1a prototype in detail - and is to be followed next week by another detailing upgrades made since, including a carrier board which adds a high-resolution LCD panel to the board.

Lesnet's full post is available on the Dangerous Prototypes blog now, while the project's forum post includes details on upgrades and modifications made since the Bus Pirate Ultra v1a design. The source code for the design, meanwhile, is available on the Dangerous Prototypes GitHub repository.

Gareth Halfacree
Freelance journalist, technical author, hacker, tinkerer, erstwhile sysadmin. For hire: freelance@halfacree.co.uk.
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