Ben C.'s Clever Compiler Imports Verilog Designs, Including a Working RISC-V CPU, Into Factorio

Software engineer Ben C. has built a tool that bridges the worlds of hardware description languages (HDLs) with construction and management sim Factorio — bringing chip designs, up to and including a working RISC-V processor, into the game.

"Shortly after Factorio 2.0 released I realized that you could probably describe combinator circuits as Verilog and have a compiler translate it," Ben C. explains of the project's inspiration. "That's what this project is. Input Verilog, output pure vanilla Factorio Blueprints. I took this new release as an opportunity to dive into a new project and a new language! At first I was just trying to learn about rust and compilers, but it evolved into a big software experiment. I added Lua scripting, a nodes-based GUI (web and native support with egui), a combinator simulator, graph partitioning, SVG generation, ILP solvers, hyper parameter optimization. Really its a bag of many things I was interested in."

Verilog is a hardware description language (HDL), a type of domain-specific language (DSL) tailored to the design of chips — either to be executed in simulation on a computer, turned into gateware for use with a field-programmable gate array (FPGA) or other programmable logic device, or taped out for production into an actual physical application-specific integrated circuit (ASIC). Factorio, meanwhile, launched in 2020 as a construction and management simulation from Wube Software — and received a major upgrade, known as Factorio 2.0, in 2024.

"To accomplish this I employ two programs," Ben. C explains. "The first is a front-end compiler to take Verilog and produce a graph of logic which can be roughly translated into Factorio logic. At the end of this process we are left with a mixture of fine-grained logic and coarse grain word-level representations. Now Rust enters the picture. I now read this JSON into what I call a 'MappedDesign;' there are some additional tweaks to make the format of a MappedDesign more favorable, but its not that important. Its essentially a deserialized Yosys output."

The compilation then turns to physical planning, using in-game combinators and wiring structures to build the design piece-by-piece. "Because the routing will place power poles," Ben C. explains, "we can reuse them for power distribution. First thing is to determine if each combinator is covered by a power distribution area, if some combinators are missing, I place a new pole to maximize coverage over missing areas. Then once I am satisfied with coverage I do a heuristic based graph traversal to try to minimize [the] number of copper wires while also making sure we only have one power distribution network. Sometimes this isn't perfect, but works well enough. I think for the RISC-V core I only needed to manually place a couple substations to get full coverage."

More details on the project are available in Ben C.'s Reddit post, while source code is available on GitHub under the GNU Affero General Public License 3; a live site hosting the back-end flow "with a GUI slapped on top," for simulation and experimentation, is available on the developer's website.