Traffic Light Controller with Verilog

This project implements a Traffic Light Controller using Verilog on an FPGA.

It was developed as one of my first practical experiments with the Sipeed Tang Primer 20K, focusing on understanding digital design, timing control, and hardware implementation.

The system controls three LEDs (Red, Yellow, and Green) following a real-world traffic light sequence.

Core concepts explored:

• Fundamentals of sequential logic in Verilog
• Counter-based timing generation
• FPGA pin mapping using Gowin IDE
• Practical LED interfacing

Schematics

The LEDs are directly connected to FPGA GPIO pins with current-limiting resistors.

How It Works

The traffic light sequence follows: RED → YELLOW → GREEN → RED

Each LED remains:

• ON for 1 second
• OFF for 0.5 seconds

Automatic continuous cycling — no reset required.

• The FPGA runs on a 27 MHz clock
• A counter generates time intervals (1s and 0.5s)
• The control logic determines which LED is active
• The sequence automatically repeats indefinitely

Synthesis and Programming

To compile and program the FPGA:

• Create a new project in Gowin IDE
• Select device GW2A-LV18PG256C8/I7
• Add the Verilog source file
• Configure the.cst constraints file with correct GPIO pins
• Run synthesis and generate the bitstream
• Program the FPGA via USB-C

Once programmed, the LEDs automatically begin cycling through the traffic sequence.

Features

• Counter-based timing control
• Continuous automatic operation
• Simulation testbench included

Future Improvements

• Add pedestrian crossing button input
• Implement adjustable timing via DIP switches
• Expand to dual-direction intersection control
• Add PWM brightness control
• Migrate to a multi-state programmable controller

Common Issues and Solutions

• Incorrect GPIO assignment: If LEDs do not light up, verify the .cst file matches the Dock pinout documentation.
• LED polarity inverted: Check if the board uses active-low outputs and adjust the logic in Verilog if necessary.

Source Code

All source files are available on GitHub:

• src/ → Verilog implementation
• constraints/ → FPGA pin mapping file
• tb/ → Simulation testbench