Karl de Boois
Published © GPL3+

Binary Neural Network Demonstration on Ultra96

FPGA-based Binary Neural Network acceleration used for Image Classification on the Avnet Ultra96 based on the Xilinx Zynq UltraScale+ MPSoC.

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Binary Neural Network Demonstration on Ultra96

Things used in this project

Hardware components

Ultra96
96Boards Ultra96
×1
MicroSD Module (Generic)
×1
Avnet Ultra96 Power Supply - 12V 2A
×1
Logitech C920 Webcam
×1
Mini DisplayPort to DisplayPort adapter
×1
Asus PB278 Monitor
×1
Zynq MMP
ZedBoard Zynq MMP
×1

Story

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Schematics

Demo Set-up

Overview diagram
Block diagram bpk5pyhf20

Code

Xilinx BNN source code for PYNQ

The BNN source code for PYNQ that is used in this project.

Credits

Karl de Boois

Karl de Boois

1 project • 5 followers
FPGA Expert with SBC addiction

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