JuergenR
Published © MIT

Automatic boot files generation for PL only projects on Zynq

Walk-through of generating the files necessary to run a Zynq based board standalone for a FPGA-only project. Vitis part uses Python script

AdvancedFull instructions provided3 hours32
Automatic boot files generation for PL only projects on Zynq

Things used in this project

Hardware components

Arty Z7-20
Digilent Arty Z7-20
×1

Software apps and online services

Vivado Design Suite
AMD Vivado Design Suite
Version 2024.2 installed on Windows
Vitis Unified Software Platform
AMD Vitis Unified Software Platform
Version 2024.2 installed on Windows

Story

Read more

Code

Main VHDL project

VHDL
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 11.03.2026 16:12:57
-- Design Name: 
-- Module Name: PLTest - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PLTest is
    Port ( clk          : in std_logic ;
           led          : out std_logic_vector (3 downto 0);
           btn          : in std_logic_vector (3 downto 0)
          );
end PLTest;

architecture Behavioral of PLTest is

subtype cnt_type is integer range 0 to 1023; 

signal debBtn: std_logic_vector (3 downto 0);

type fsel_states is (fReset, fWait, fTrigger);
signal fsel_state:          fsel_states := fReset;
signal fselect:             cnt_type := 0;
signal ftrig:               std_logic;

-- debug definitions
--attribute mark_debug : string;
--attribute mark_debug of debBtn: signal is "true";
--attribute mark_debug of fsel_state: signal is "true";
--attribute mark_debug of fselect: signal is "true";
--attribute mark_debug of ftrig: signal is "true";

component debounce is
  PORT (
    clk : IN STD_LOGIC;
    resetn : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    dout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
  );
end component debounce;

component EdgeDetect
	port(
		clk			: in std_logic;
		reset		: in std_logic;
		level		: in std_logic;
		tick_rise	: out std_logic;
		tick_fall	: out std_logic
	);
end component;

begin
    -- debounce inputs and edge detection
    c_deb_btn : debounce
    PORT MAP (
      clk => clk,
      resetn => '1',
      din => btn,
      dout => debBtn
    );

    c_fsel_edge: EdgeDetect
 	port map(
        clk          => clk,
        reset        => '0',
        level        => debBtn(0),
        tick_rise    => ftrig,
        tick_fall    => open
    );
   

    led(1 downto 0) <= std_logic_vector(to_unsigned(fselect, 2));
    led(3 downto 2) <= debBtn(3 downto 2);
    
    p_f_select: process(clk)
    begin
    if rising_edge(clk) then
        case fsel_state is
            when fReset =>
                fselect <= 0;
                fsel_state <= fWait; 
            when fWait =>
                if ftrig = '1' then
                    fsel_state <= fTrigger;
                end if;
            when fTrigger => 
                if fselect = 3 then
                    fselect <= 0;
                else
                    fselect <= fselect + 1;
                end if;
                fsel_state <= fWait;
        end case;
    end if;
    end process;




end Behavioral;

Edge Detection component

VHDL
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:25:31 04/10/2012 
-- Design Name: 
-- Module Name:    EdgeDetect - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--   edge detector for both rising and falling edge
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity EdgeDetect is
	port(
		clk			: in std_logic;
		reset		: in std_logic;
		level		: in std_logic;
		tick_rise	: out std_logic;
		tick_fall	: out std_logic
	);
end EdgeDetect;

architecture Behavioral of EdgeDetect is

signal delay_reg: std_ulogic;

begin
   -- delay register
	process(clk,reset)
	begin
		if (clk'event and clk='1') then
			if (reset='1') then
				delay_reg <= '0';
			else
				delay_reg <= level;
			end if;
		end if;
   end process;
   -- decoding logic
   tick_rise <= (not delay_reg) and level;
   tick_fall <= delay_reg and (not level);

end Behavioral;

Debounce component

VHDL
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 03/27/2020 03:31:33 PM
-- Design Name: 
-- Module Name: debounce - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity debounce is
    generic (
        NCNT        : integer := 20;        --counting size: 2^N * 10ns = 10.5ms tick
        W           : integer := 4;         -- word width of input data
        DBCNT       : integer := 3          -- debouncing shift length
    );
    port(
        clk         : in std_logic;
        resetn		: in std_logic;
        din			: in std_logic_vector(W-1 downto 0);			--bouncing input
        dout		: out std_logic_vector(W-1 downto 0)			--debounced output
    );
end debounce;

architecture Behavioral of debounce is
    type memory_type is array (natural range <>) of std_logic_vector(W-1 downto 0);
    signal fifo_memory  : memory_type(0 to DBCNT);
    signal andedData    : std_logic_vector(W-1 downto 0);
    signal oredData    : std_logic_vector(W-1 downto 0);
    signal dbStateNxt   : std_logic_vector(W-1 downto 0);
    signal dbStateReg   : std_logic_vector(W-1 downto 0);
    signal cnt_reg      : unsigned(NCNT-1 downto 0);
    signal cnt_nxt      : unsigned(NCNT-1 downto 0);
    signal cnt_tick     : std_logic;
    signal reset        : std_logic;

	function or_reduction (vec : in memory_type) return std_logic_vector is           
	  variable res_v : std_logic_vector(W-1 downto 0) := (others => '0');    
	  begin                                                                         
	  for i in vec'range loop                                                       
	    res_v := res_v or vec(i);                                                   
	  end loop;                                                                     
	  return res_v;                                                                 
	end function;                                                                   

	function and_reduction (vec : in memory_type) return std_logic_vector is           
	  variable res_v : std_logic_vector(W-1 downto 0) := (others => '1');    
	  begin                                                                         
	  for i in vec'range loop                                                       
	    res_v := res_v and vec(i);                                                   
	  end loop;                                                                     
	  return res_v;                                                                 
	end function;                                                                   

begin
    reset <= not resetn;
    cntr: process(clk, reset)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                cnt_reg <= (others =>'1');
            else
                cnt_reg <= cnt_nxt;
            end if;
        end if;
    end process cntr;
    
    -- next-state logic and output tick
    cnt_nxt <= cnt_reg + 1;
    cnt_tick <= '1' when cnt_reg=0 else '0';

    fifo_store: process (clk, cnt_tick, reset) 
    begin
        if rising_edge(clk) then
            if reset = '1' then
                fifo_memory <= (others => (others => '0'));
            elsif cnt_tick = '1' then
                fifo_memory <= din & fifo_memory(0 to DBCNT-1);
            end if;
        end if;
    end process fifo_store;

    debounce_state: process(clk, cnt_tick, reset)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                dbStateReg <= (others => '0');
                andedData <= (others => '0');
                oredData <= (others => '0');
            elsif cnt_tick = '1' then
                andedData <= and_reduction(fifo_memory);
                oredData <= or_reduction(fifo_memory);
                dbStateReg <= (andedData and not dbStateReg) or (oredData and dbStateReg);
            end if;
        end if;
    end process debounce_state;
    
--    debounce_next: process(fifo_memory)
--    begin
--        andedData <= and_reduction(fifo_memory);
--        oredData <= or_reduction(fifo_memory);
--        dbStateNxt <= (andedData and not dbStateReg) or (oredData and dbStateReg);
--    end process debounce_next;
    
    -- output signal
    dout <= dbStateReg;

end Behavioral;

Boot generation script

Python
No preview (download only).

Credits

JuergenR
2 projects • 3 followers
Electrical and Software engineer in machine building industry.
Thanks to Dom (www.youtube.com/@Dom-bo8wd) and Digilent.

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