Hardware components | ||||||
| × | 1 | ||||
Software apps and online services | ||||||
| ||||||
| ||||||
In this tutorial I will show how to create and use the example project for the GTH transceivers in the Zynq Ultrascale+ XCZU4EV.
The board I'm using is the MYD-CZU4EV by MYIR, with an AMD XCZU4EV and a QSFP+ cage ready to connect an SFP+ cable.
The board used in this project
Vivado includes the Ultrascale FPGA Transceivers Wizard that creates a series of VHDL/ Verilog files that can be customized for a wide range of purposes.
There are two ways to use the wizard:
1. Configure it and generate an xci file to be instantiated using the templates provided.
2. Configure it and create an example project to examine and change the created RTL files
The second approach is more versatile and more appropriate for a first time using the GTH trasceivers. Experienced users may directly use the xci in their project (although the rest of the code probably came from the example project!)
Configuring the transceiverDouble click on the Transceiver wizard on the IP catalog, the configuration GUI will appear.
The GUI comes with a large number of presets from the Transceiver Configuration Preset dropdown. For this tutorial, choose the GTH-10BASE-R preset:
Make sure that the Actual Reference Clock matches the clock on the board (156.25 MHz), by selecting one of the available values.
Moving to the second tab, Physical Resources, the two bottom channels are selected and reference clock selected is MGTREFCLK1. This is important because MGTREFCLK0 is not connected to any clock generator in this development board.
Note the frequency of the free-running clock (250 MHz), that will be used later on.
The optional Features tab can be skipped and left as it is. On the structural Options tab, we just need to select the inclusion of the in-system IBERT core:
After all these changes click OK to close the GUI.
Create the example projectThe example project needs a few tweaks:
1. It needs a free-running clock, in this case 250 MHz. Because the MYD board doesn't have any clock fed into the PL, the PS is used. However, it has to be started, for example running a hello world application.
2. The generated block has some I/O that need to be connected. In this case, they are connected to a VIO (Virtual I/O) for direct user interaction with Hardware Manager.
3. Each SFP+ has a Tx enable pin, that are here also tied to the VIO.
After the xci is created, right-click on it and select Open IP example Design
In the Vivado project created, create a new Block Diagram and add to it a Processor System IP:
Double click on the IP block and click on Presets > Apply configuration:
Browse for the file myd_gth_ps_config.tcl (included). Click OK to close the GUI.
Drag and drop the source file gtwizard_ultrascale_0_example_top into the block diagram:
Select all the transceiver RX and TX pins as well as the Reference Clock input and make them external (Ctrl + T or right click > Make External)
Next, add a VIO (Virtual I/O) from the IP catalog and configure it for 2 inputs and 4 outputs.
Connect pl_clk1 (not pl_clk0 !) to the VIO clk pin and the transceivers freerun clk input.
Connect the two outputs of the transceivers block to the VIO inputs.
Connect two of the VIO outputs to the transceiver block inputs.
Finally, make the other two VIO outputs external and rename them as Tx_Ena_LT and Tx_Ena_RT:
Now right click on the block diagram in the sources panel and select Create HDL wrapper
If the wrapper is not automatically the top file, right click on it and set it as top:
Click on Run Synthesis, then open the synthesized design. If the Package view doesn't appear, cselect it from the drop down on the top right corner.
Note the the transceiver pins are already assigned as they are fixed. The additional pins have to be located.
Place Tx_Ena_LT on AF5 and TxEna_RT on H2, following the boards pinout:
These signals will enable the Left Top and Right Top SFP+ in the cage, here is the schematic (for Left Top):
Place the pins, change the standard to LVCMOS1V8 and set the external termination to NONE:
Save the changes with CTRL+S and enter a name for the new constraints file to be created (or it could also be added to the existing one):
Last thing to do is to comment out line 80 in the constraints file gtwizard_ultrascale_0_example_top.xdc
This is because this clock comes from the PS and it is already defined.
Click on Generate Bitstream. This will re-run synthesis and run implementation.
Finally, click on File > Export to create the XSA file to use with Vitis.
Create the PS softwareStart Vitis and create a workspace. Create a platform project with the XSA generated before. Choose standalone OS and A53 core, and generate boot components.
Create an Application project and use the Hello World template. Build the whole system and check that BOOT.BIN is generated under debug > sd_card:
Copy the BOOT.BIN file to an SD card with FAT format and insert it on the MYD board.
Check that the Boot Mode switches are set for SD boot (TF marked on the board).
Connect an USB cable from the Debug Uart USB to a computer.
Connect a JTAG cable from the JTAG to a computer.
On the computer, start a terminal application, like TeraTerm.
Power the board on, the terminal should look like this:
Now on Vivado open Hardware Manager and click on Open Target, select Autoconnect. It should see the IBERT, both active MGT and the (unpopulated) VIO:
On each VIO tab, click on the '+' button and add all signals. If you prefer, change all outputs to toggle.
Create links and use IBERT
Click on Create Links and on the GUI, select MGT_X0Y4 for both TX and RX side and click '+' under New Links
Right click on the link created and select Create Scan:
Leave the default settings and click OK:
You should get an eye diagram like this....
Which is bad! The reason is the Tx hasn't been enabled. In the VIO tab, set both Tx_Enable high. Note how the link_status_out goes high.
Now re-run the scan:
And now we get a nice eye diagram at 10.3 Gbps
By reducing the horizontal and vertical increments, a better resolution is obtained:
SFP+ modules have an I2C interface for identification and configuration. The MYD board has connections to the four SFP+ cages via an I2C multiplexer. Optimizing the SFP+ module settings and monitoring the status via I2C will be for another article.
proc getPresetInfo {} {
return [dict create name {myd_gth_ps_config} description {myd_gth_ps_config} vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 display_name {myd_gth_ps_config} ]
}
proc validate_preset {IPINST} { return true }
proc apply_preset {IPINST} {
return [dict create \
CONFIG.PSU_VALUE_SILVERSION {3} \
CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.33333333} \
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__CAN0__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__DPAUX__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ACT_DDR_FREQ_MHZ {1200.000000} \
CONFIG.PSU__GEM__TSU__ENABLE {0} \
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
CONFIG.PSU__ENET0__PTP__ENABLE {0} \
CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
CONFIG.PSU__ENET1__PTP__ENABLE {0} \
CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
CONFIG.PSU__FPGA_PL1_ENABLE {1} \
CONFIG.PSU__FPGA_PL2_ENABLE {0} \
CONFIG.PSU__FPGA_PL3_ENABLE {0} \
CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
CONFIG.PSU__ENET2__PTP__ENABLE {0} \
CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
CONFIG.PSU__ENET3__PTP__ENABLE {0} \
CONFIG.PSU__ENET3__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET3__GRP_MDIO__IO {<Select>} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO2_MIO__IO {<Select>} \
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C0__PERIPHERAL__IO {EMIO} \
CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 24 .. 25} \
CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
CONFIG.PSU__GT__LINK_SPEED {<Select>} \
CONFIG.PSU__GT__VLT_SWNG_LVL_4 {} \
CONFIG.PSU__GT__PRE_EMPH_LVL_4 {} \
CONFIG.PSU__USB0__REF_CLK_SEL {<Select>} \
CONFIG.PSU__USB0__REF_CLK_FREQ {<Select>} \
CONFIG.PSU__USB1__REF_CLK_SEL {<Select>} \
CONFIG.PSU__USB1__REF_CLK_FREQ {<Select>} \
CONFIG.PSU__DP__REF_CLK_SEL {<Select>} \
CONFIG.PSU__DP__REF_CLK_FREQ {<Select>} \
CONFIG.PSU__SATA__REF_CLK_SEL {<Select>} \
CONFIG.PSU__SATA__REF_CLK_FREQ {<Select>} \
CONFIG.PSU__DP__LANE_SEL {<Select>} \
CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
CONFIG.PSU__PCIE__BAR0_64BIT {0} \
CONFIG.PSU__PCIE__BAR0_VAL {} \
CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
CONFIG.PSU__PCIE__BAR1_64BIT {0} \
CONFIG.PSU__PCIE__BAR1_VAL {} \
CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
CONFIG.PSU__PCIE__BAR2_64BIT {0} \
CONFIG.PSU__PCIE__BAR2_VAL {} \
CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
CONFIG.PSU__PCIE__BAR3_64BIT {0} \
CONFIG.PSU__PCIE__BAR3_VAL {} \
CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
CONFIG.PSU__PCIE__BAR4_64BIT {0} \
CONFIG.PSU__PCIE__BAR4_VAL {} \
CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
CONFIG.PSU__PCIE__BAR5_64BIT {0} \
CONFIG.PSU__PCIE__BAR5_VAL {} \
CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__EROM_ENABLE {0} \
CONFIG.PSU__PCIE__EROM_VAL {} \
CONFIG.PSU__PCIE__VENDOR_ID {} \
CONFIG.PSU__PCIE__DEVICE_ID {} \
CONFIG.PSU__PCIE__REVISION_ID {} \
CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \
CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
CONFIG.PSU__PCIE__ECRC_ERR {0} \
CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
CONFIG.PSU__PCIE__MULTIHEADER {0} \
CONFIG.PSU__PCIE__ECRC_CHECK {0} \
CONFIG.PSU__PCIE__ECRC_GEN {0} \
CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
CONFIG.PSU__PCIE__INTX_GENERATION {0} \
CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
CONFIG.PSU_IMPORT_BOARD_PRESET {} \
CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
CONFIG.PSU__PROTECTION__DEBUG {0} \
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
CONFIG.PSU__PROTECTION__ENABLE {0} \
CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
CONFIG.PSU__EP__IP {0} \
CONFIG.PSU__ACTUAL__IP {1} \
CONFIG.SUBPRESET2 {Custom} \
CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 1#I2C 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1##########################} \
CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#gpio0[6]#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#scl_out#sda_out#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpio1[32]#gpio1[33]#rxd#txd#gpio1[36]#gpio1[37]#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#gpio1[43]#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out##########################} \
CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \
CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \
CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
CONFIG.PSU__PMU__GPI0__ENABLE {0} \
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
CONFIG.PSU__PMU__GPO0__ENABLE {0} \
CONFIG.PSU__PMU__GPO1__ENABLE {0} \
CONFIG.PSU__PMU__GPO2__ENABLE {0} \
CONFIG.PSU__PMU__GPO3__ENABLE {0} \
CONFIG.PSU__PMU__GPO4__ENABLE {0} \
CONFIG.PSU__PMU__GPO5__ENABLE {0} \
CONFIG.PSU__PMU__GPI0__IO {<Select>} \
CONFIG.PSU__PMU__GPO0__IO {<Select>} \
CONFIG.PSU__PMU__GPO1__IO {<Select>} \
CONFIG.PSU__PMU__GPO2__IO {<Select>} \
CONFIG.PSU__PMU__GPO2__POLARITY {high} \
CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 22} \
CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
CONFIG.PSU__SD0__GRP_CD__IO {<Select>} \
CONFIG.PSU__SD0__GRP_POW__ENABLE {1} \
CONFIG.PSU__SD0__GRP_POW__IO {MIO 23} \
CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
CONFIG.PSU__SD0__SLOT_TYPE {eMMC} \
CONFIG.PSU__SD0__RESET__ENABLE {1} \
CONFIG.PSU__SD0__DATA_TRANSFER_MODE {8Bit} \
CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \
CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x6} \
CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x12} \
CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x6} \
CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x0} \
CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
CONFIG.PSU__SD1__RESET__ENABLE {0} \
CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
CONFIG.PSU__SD1__CLK_50_SDR_ITAP_DLY {0x15} \
CONFIG.PSU__SD1__CLK_50_SDR_OTAP_DLY {0x5} \
CONFIG.PSU__SD1__CLK_50_DDR_ITAP_DLY {0x0} \
CONFIG.PSU__SD1__CLK_50_DDR_OTAP_DLY {0x0} \
CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x0} \
CONFIG.PSU__SD1__CLK_200_SDR_OTAP_DLY {0x0} \
CONFIG.PSU__DEVICE_TYPE {EV} \
CONFIG.PSU_SMC_CYCLE_T0 {NA} \
CONFIG.PSU_SMC_CYCLE_T1 {NA} \
CONFIG.PSU_SMC_CYCLE_T2 {NA} \
CONFIG.PSU_SMC_CYCLE_T3 {NA} \
CONFIG.PSU_SMC_CYCLE_T4 {NA} \
CONFIG.PSU_SMC_CYCLE_T5 {NA} \
CONFIG.PSU_SMC_CYCLE_T6 {NA} \
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SPI0__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS0__IO {<Select>} \
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SPI1__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS0__IO {<Select>} \
CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
CONFIG.PSU__UART0__BAUD_RATE {115200} \
CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
CONFIG.PSU__UART1__BAUD_RATE {<Select>} \
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
CONFIG.PSU__DDRC__AL {0} \
CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
CONFIG.PSU__DDRC__CL {16} \
CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
CONFIG.PSU__DDRC__CWL {12} \
CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \
CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
CONFIG.PSU__DDRC__ECC {Disabled} \
CONFIG.PSU__DDRC__ECC_SCRUB {0} \
CONFIG.PSU__DDRC__ENABLE {1} \
CONFIG.PSU__DDRC__FREQ_MHZ {1} \
CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400R} \
CONFIG.PSU__DDRC__T_FAW {30.0} \
CONFIG.PSU__DDRC__T_RAS_MIN {32.0} \
CONFIG.PSU__DDRC__T_RC {45.32} \
CONFIG.PSU__DDRC__T_RCD {16} \
CONFIG.PSU__DDRC__T_RP {16} \
CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
CONFIG.PSU__DDRC__VREF {1} \
CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
CONFIG.PSU__DDRC__PLL_BYPASS {0} \
CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
CONFIG.PSU__DDRC__COMPONENTS {Components} \
CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
CONFIG.PSU__DDRC__FGRM {1X} \
CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
CONFIG.PSU__DDRC__SB_TARGET {16-16-16} \
CONFIG.PSU__DDRC__LP_ASR {manual normal} \
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {1} \
CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
CONFIG.PSU__DDR_QOS_ENABLE {0} \
CONFIG.PSU__DDR_QOS_PORT0_TYPE {<Select>} \
CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {<Select>} \
CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {<Select>} \
CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {<Select>} \
CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {<Select>} \
CONFIG.PSU__DDR_QOS_PORT3_TYPE {<Select>} \
CONFIG.PSU__DDR_QOS_PORT4_TYPE {<Select>} \
CONFIG.PSU__DDR_QOS_PORT5_TYPE {<Select>} \
CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \
CONFIG.PSU__FP__POWER__ON {1} \
CONFIG.PSU__PL__POWER__ON {1} \
CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
CONFIG.PSU__TCM0A__POWER__ON {1} \
CONFIG.PSU__TCM0B__POWER__ON {1} \
CONFIG.PSU__TCM1A__POWER__ON {1} \
CONFIG.PSU__TCM1B__POWER__ON {1} \
CONFIG.PSU__RPU__POWER__ON {1} \
CONFIG.PSU__L2_BANK0__POWER__ON {1} \
CONFIG.PSU__GPU_PP0__POWER__ON {1} \
CONFIG.PSU__GPU_PP1__POWER__ON {1} \
CONFIG.PSU__ACPU0__POWER__ON {1} \
CONFIG.PSU__ACPU1__POWER__ON {1} \
CONFIG.PSU__ACPU2__POWER__ON {1} \
CONFIG.PSU__ACPU3__POWER__ON {1} \
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 34 .. 35} \
CONFIG.PSU__UART0__MODEM__ENABLE {0} \
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__UART1__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__UART1__MODEM__ENABLE {0} \
CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USB0__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__USB0__RESET__ENABLE {0} \
CONFIG.PSU__USB__RESET__MODE {<Select>} \
CONFIG.PSU__USB__RESET__POLARITY {<Select>} \
CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USB1__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__USB1__RESET__ENABLE {0} \
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USB3_0__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USB3_1__PERIPHERAL__IO {<Select>} \
CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
CONFIG.PSU__USE__ADMA {0} \
CONFIG.PSU__USE__M_AXI_GP0 {0} \
CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \
CONFIG.PSU__USE__M_AXI_GP1 {0} \
CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
CONFIG.PSU__USE__M_AXI_GP2 {0} \
CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
CONFIG.PSU__USE__S_AXI_ACP {0} \
CONFIG.PSU__USE__S_AXI_GP0 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \
CONFIG.PSU__SAXIGP0__DATA_WIDTH {64} \
CONFIG.PSU__USE__S_AXI_GP1 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \
CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \
CONFIG.PSU__USE__S_AXI_GP2 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
CONFIG.PSU__USE__S_AXI_GP3 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
CONFIG.PSU__USE__S_AXI_GP4 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
CONFIG.PSU__USE__S_AXI_GP5 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \
CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \
CONFIG.PSU__USE__S_AXI_GP6 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \
CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \
CONFIG.PSU__USE__S_AXI_ACE {0} \
CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \
CONFIG.PSU__EN_EMIO_TRACE {0} \
CONFIG.PSU__USE__AUDIO {0} \
CONFIG.PSU__USE__VIDEO {0} \
CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
CONFIG.PSU__USE__FTM {0} \
CONFIG.PSU__USE__CROSS_TRIGGER {0} \
CONFIG.PSU__FTM__CTI_IN_0 {0} \
CONFIG.PSU__FTM__CTI_IN_1 {0} \
CONFIG.PSU__FTM__CTI_IN_2 {0} \
CONFIG.PSU__FTM__CTI_IN_3 {0} \
CONFIG.PSU__FTM__CTI_OUT_0 {0} \
CONFIG.PSU__FTM__CTI_OUT_1 {0} \
CONFIG.PSU__FTM__CTI_OUT_2 {0} \
CONFIG.PSU__FTM__CTI_OUT_3 {0} \
CONFIG.PSU__FTM__GPO {0} \
CONFIG.PSU__FTM__GPI {0} \
CONFIG.PSU__USE__GDMA {0} \
CONFIG.PSU__USE__IRQ {0} \
CONFIG.PSU__USE__IRQ0 {1} \
CONFIG.PSU__USE__IRQ1 {0} \
CONFIG.PSU__USE__CLK0 {0} \
CONFIG.PSU__USE__CLK1 {0} \
CONFIG.PSU__USE__CLK2 {0} \
CONFIG.PSU__USE__CLK3 {0} \
CONFIG.PSU__USE__RST0 {0} \
CONFIG.PSU__USE__RST1 {0} \
CONFIG.PSU__USE__RST2 {0} \
CONFIG.PSU__USE__RST3 {0} \
CONFIG.PSU__USE__FABRIC__RST {1} \
CONFIG.PSU__USE__RTC {0} \
CONFIG.PSU__PRESET_APPLIED {0} \
CONFIG.PSU__USE__EVENT_RPU {0} \
CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
CONFIG.PSU__USE__STM {0} \
CONFIG.PSU__USE__DEBUG__TEST {0} \
CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \
CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
CONFIG.PSU__EXPAND__CORESIGHT {0} \
CONFIG.PSU__EXPAND__GIC {0} \
CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_0_POLARITY {Default} \
CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_0_SLEW {fast} \
CONFIG.PSU_MIO_0_DIRECTION {out} \
CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_1_POLARITY {Default} \
CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_1_SLEW {fast} \
CONFIG.PSU_MIO_1_DIRECTION {inout} \
CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_2_POLARITY {Default} \
CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_2_SLEW {fast} \
CONFIG.PSU_MIO_2_DIRECTION {inout} \
CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_3_POLARITY {Default} \
CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_3_SLEW {fast} \
CONFIG.PSU_MIO_3_DIRECTION {inout} \
CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_4_POLARITY {Default} \
CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_4_SLEW {fast} \
CONFIG.PSU_MIO_4_DIRECTION {inout} \
CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_5_POLARITY {Default} \
CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_5_SLEW {fast} \
CONFIG.PSU_MIO_5_DIRECTION {out} \
CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_6_POLARITY {Default} \
CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_6_SLEW {fast} \
CONFIG.PSU_MIO_6_DIRECTION {inout} \
CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_7_POLARITY {Default} \
CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_7_SLEW {fast} \
CONFIG.PSU_MIO_7_DIRECTION {out} \
CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_8_POLARITY {Default} \
CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_8_SLEW {fast} \
CONFIG.PSU_MIO_8_DIRECTION {inout} \
CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_9_POLARITY {Default} \
CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_9_SLEW {fast} \
CONFIG.PSU_MIO_9_DIRECTION {inout} \
CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_10_POLARITY {Default} \
CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_10_SLEW {fast} \
CONFIG.PSU_MIO_10_DIRECTION {inout} \
CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_11_POLARITY {Default} \
CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_11_SLEW {fast} \
CONFIG.PSU_MIO_11_DIRECTION {inout} \
CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_12_POLARITY {Default} \
CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_12_SLEW {fast} \
CONFIG.PSU_MIO_12_DIRECTION {out} \
CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_13_POLARITY {Default} \
CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_13_SLEW {fast} \
CONFIG.PSU_MIO_13_DIRECTION {inout} \
CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_14_POLARITY {Default} \
CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_14_SLEW {fast} \
CONFIG.PSU_MIO_14_DIRECTION {inout} \
CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_15_POLARITY {Default} \
CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_15_SLEW {fast} \
CONFIG.PSU_MIO_15_DIRECTION {inout} \
CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_16_POLARITY {Default} \
CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_16_SLEW {fast} \
CONFIG.PSU_MIO_16_DIRECTION {inout} \
CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_17_POLARITY {Default} \
CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_17_SLEW {fast} \
CONFIG.PSU_MIO_17_DIRECTION {inout} \
CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_18_POLARITY {Default} \
CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_18_SLEW {fast} \
CONFIG.PSU_MIO_18_DIRECTION {inout} \
CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_19_POLARITY {Default} \
CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_19_SLEW {fast} \
CONFIG.PSU_MIO_19_DIRECTION {inout} \
CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_20_POLARITY {Default} \
CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_20_SLEW {fast} \
CONFIG.PSU_MIO_20_DIRECTION {inout} \
CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_21_POLARITY {Default} \
CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_21_SLEW {fast} \
CONFIG.PSU_MIO_21_DIRECTION {inout} \
CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_22_POLARITY {Default} \
CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_22_SLEW {fast} \
CONFIG.PSU_MIO_22_DIRECTION {out} \
CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_23_POLARITY {Default} \
CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_23_SLEW {fast} \
CONFIG.PSU_MIO_23_DIRECTION {out} \
CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_24_POLARITY {Default} \
CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_24_SLEW {fast} \
CONFIG.PSU_MIO_24_DIRECTION {inout} \
CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_25_POLARITY {Default} \
CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_25_SLEW {fast} \
CONFIG.PSU_MIO_25_DIRECTION {inout} \
CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_26_POLARITY {Default} \
CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_26_SLEW {slow} \
CONFIG.PSU_MIO_26_DIRECTION {inout} \
CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_27_POLARITY {Default} \
CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_27_SLEW {fast} \
CONFIG.PSU_MIO_27_DIRECTION {inout} \
CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_28_POLARITY {Default} \
CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_28_SLEW {fast} \
CONFIG.PSU_MIO_28_DIRECTION {inout} \
CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_29_POLARITY {Default} \
CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_29_SLEW {fast} \
CONFIG.PSU_MIO_29_DIRECTION {inout} \
CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_30_POLARITY {Default} \
CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_30_SLEW {fast} \
CONFIG.PSU_MIO_30_DIRECTION {inout} \
CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_31_POLARITY {Default} \
CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_31_SLEW {slow} \
CONFIG.PSU_MIO_31_DIRECTION {inout} \
CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_32_POLARITY {Default} \
CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_32_SLEW {slow} \
CONFIG.PSU_MIO_32_DIRECTION {inout} \
CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_33_POLARITY {Default} \
CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_33_SLEW {slow} \
CONFIG.PSU_MIO_33_DIRECTION {inout} \
CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_34_POLARITY {Default} \
CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_34_SLEW {fast} \
CONFIG.PSU_MIO_34_DIRECTION {in} \
CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_35_POLARITY {Default} \
CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_35_SLEW {fast} \
CONFIG.PSU_MIO_35_DIRECTION {out} \
CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_36_POLARITY {Default} \
CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_36_SLEW {slow} \
CONFIG.PSU_MIO_36_DIRECTION {inout} \
CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_37_POLARITY {Default} \
CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_37_SLEW {slow} \
CONFIG.PSU_MIO_37_DIRECTION {inout} \
CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_38_POLARITY {Default} \
CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_38_SLEW {slow} \
CONFIG.PSU_MIO_38_DIRECTION {inout} \
CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_39_POLARITY {Default} \
CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_39_SLEW {slow} \
CONFIG.PSU_MIO_39_DIRECTION {inout} \
CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_40_POLARITY {Default} \
CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_40_SLEW {slow} \
CONFIG.PSU_MIO_40_DIRECTION {inout} \
CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_41_POLARITY {Default} \
CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_41_SLEW {slow} \
CONFIG.PSU_MIO_41_DIRECTION {inout} \
CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_42_POLARITY {Default} \
CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_42_SLEW {slow} \
CONFIG.PSU_MIO_42_DIRECTION {inout} \
CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_43_POLARITY {Default} \
CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_43_SLEW {slow} \
CONFIG.PSU_MIO_43_DIRECTION {inout} \
CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_44_POLARITY {Default} \
CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_44_SLEW {fast} \
CONFIG.PSU_MIO_44_DIRECTION {in} \
CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_45_POLARITY {Default} \
CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_45_SLEW {fast} \
CONFIG.PSU_MIO_45_DIRECTION {in} \
CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_46_POLARITY {Default} \
CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_46_SLEW {fast} \
CONFIG.PSU_MIO_46_DIRECTION {inout} \
CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_47_POLARITY {Default} \
CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_47_SLEW {fast} \
CONFIG.PSU_MIO_47_DIRECTION {inout} \
CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_48_POLARITY {Default} \
CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_48_SLEW {fast} \
CONFIG.PSU_MIO_48_DIRECTION {inout} \
CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_49_POLARITY {Default} \
CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_49_SLEW {fast} \
CONFIG.PSU_MIO_49_DIRECTION {inout} \
CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_50_POLARITY {Default} \
CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_50_SLEW {fast} \
CONFIG.PSU_MIO_50_DIRECTION {inout} \
CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_51_POLARITY {Default} \
CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_51_SLEW {fast} \
CONFIG.PSU_MIO_51_DIRECTION {out} \
CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_52_POLARITY {Default} \
CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_52_SLEW {fast} \
CONFIG.PSU_MIO_52_DIRECTION {in} \
CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_53_POLARITY {Default} \
CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_53_SLEW {fast} \
CONFIG.PSU_MIO_53_DIRECTION {in} \
CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_54_POLARITY {Default} \
CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_54_SLEW {fast} \
CONFIG.PSU_MIO_54_DIRECTION {inout} \
CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_55_POLARITY {Default} \
CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_55_SLEW {fast} \
CONFIG.PSU_MIO_55_DIRECTION {in} \
CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_56_POLARITY {Default} \
CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_56_SLEW {fast} \
CONFIG.PSU_MIO_56_DIRECTION {inout} \
CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_57_POLARITY {Default} \
CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_57_SLEW {fast} \
CONFIG.PSU_MIO_57_DIRECTION {inout} \
CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_58_POLARITY {Default} \
CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_58_SLEW {fast} \
CONFIG.PSU_MIO_58_DIRECTION {out} \
CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_59_POLARITY {Default} \
CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_59_SLEW {fast} \
CONFIG.PSU_MIO_59_DIRECTION {inout} \
CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_60_POLARITY {Default} \
CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_60_SLEW {fast} \
CONFIG.PSU_MIO_60_DIRECTION {inout} \
CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_61_POLARITY {Default} \
CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_61_SLEW {fast} \
CONFIG.PSU_MIO_61_DIRECTION {inout} \
CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_62_POLARITY {Default} \
CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_62_SLEW {fast} \
CONFIG.PSU_MIO_62_DIRECTION {inout} \
CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_63_POLARITY {Default} \
CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_63_SLEW {fast} \
CONFIG.PSU_MIO_63_DIRECTION {inout} \
CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_64_POLARITY {Default} \
CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_64_SLEW {fast} \
CONFIG.PSU_MIO_64_DIRECTION {out} \
CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_65_POLARITY {Default} \
CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_65_SLEW {fast} \
CONFIG.PSU_MIO_65_DIRECTION {out} \
CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_66_POLARITY {Default} \
CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_66_SLEW {fast} \
CONFIG.PSU_MIO_66_DIRECTION {out} \
CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_67_POLARITY {Default} \
CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_67_SLEW {fast} \
CONFIG.PSU_MIO_67_DIRECTION {out} \
CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_68_POLARITY {Default} \
CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_68_SLEW {fast} \
CONFIG.PSU_MIO_68_DIRECTION {out} \
CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_69_POLARITY {Default} \
CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_69_SLEW {fast} \
CONFIG.PSU_MIO_69_DIRECTION {out} \
CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_70_POLARITY {Default} \
CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_70_SLEW {fast} \
CONFIG.PSU_MIO_70_DIRECTION {in} \
CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_71_POLARITY {Default} \
CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_71_SLEW {fast} \
CONFIG.PSU_MIO_71_DIRECTION {in} \
CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_72_POLARITY {Default} \
CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_72_SLEW {fast} \
CONFIG.PSU_MIO_72_DIRECTION {in} \
CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_73_POLARITY {Default} \
CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_73_SLEW {fast} \
CONFIG.PSU_MIO_73_DIRECTION {in} \
CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_74_POLARITY {Default} \
CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_74_SLEW {fast} \
CONFIG.PSU_MIO_74_DIRECTION {in} \
CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_75_POLARITY {Default} \
CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_75_SLEW {fast} \
CONFIG.PSU_MIO_75_DIRECTION {in} \
CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_76_POLARITY {Default} \
CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_76_SLEW {fast} \
CONFIG.PSU_MIO_76_DIRECTION {out} \
CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_77_POLARITY {Default} \
CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \
CONFIG.PSU_MIO_77_SLEW {fast} \
CONFIG.PSU_MIO_77_DIRECTION {inout} \
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
...
This file has been truncated, please download it to see its full contents.
14 projects • 31 followers
Electronics engineer focused on FPGA for accelerated computing and ML but with a wide background in electronics design and software design
Comments