FPGA DSP: FIR Filter with DDS Compiler in Vivado

Introduction

Generate three signals with DDS compiler, and implement lowpass filter in Vivado. The lowpass filter will filter the faster signal.

The tutorial is divided into several key sections:

Signal Generation: Shows how to use the DDS (Direct Digital Synthesis) compiler to generate test signals - a 10 MHz signal and a 500 kHz signal, which are then combined to create a mixed signal for testing.

FIR Filter Design: Explains the key factors affecting FIR filter performance, including:

• Number of taps and their impact on filter response
• Quantization and coefficient bit width considerations
• Resource utilization trade-offs
• Implementation: Demonstrates the practical implementation using Vivado, including
• Setting up the FIR Compiler IP
• Configuring filter parameters using MATLAB-generated coefficients
• Setting up proper bit widths and clock frequencies
• Adding necessary components like clock sources and ILA (Integrated Logic Analyzer)

Testing and Verification: Shows how to verify the filter's operation through:

Simulation results showing the filtering of high-frequency components

Hardware implementation on a ZCU-104 board

A special technique to observe the filter's impulse response using a counter-based impulse generator

You can find the full Video here

Part 1: DDS compiler setup to generate two signals and mixed signal

Let's begin by generating the signals for our test-bench:

• Add a DDS Compiler to the block design. In the Configuration tab, set the system clock to 100 MHz.

• Since we only need to generate sine waves, in the Implementation tab, select the Sine option for the output and deselect has phase output options. In the Output Frequency tab, set the frequency for Channel 1 to 500 kHz.

• Add another DDS Compiler to the block design. Repeat the same setup, but this time set the output frequency to 10 MHz.

• Add an Adder to the design. Set its input bit width to 8, and its output bit width to 9.

• Connect the outputs of both DDS Compilers to the input of the Adder. This will generate the mixed signal.
• Add a simulation clock generator to the design and set its frequency to 100MHz. this frequency will be also the sample rate of the design

DDS compiler simulation results:

As shown in the simulation results:

• The first sine wave has a period of 2000 ns, confirming it is a 500 kHz signal.
• The second sine wave has a period of 100 ns, confirming it is a 10 MHz signal.

You can also observe the mixed signal, where the faster signal fluctuates in amplitude at the frequency of the slower signal, demonstrating the combination of the two frequencies.

Vivado FIR filter simulation

FIR Filter Configuration:The performance of an F-IR filter is influenced by several key factors:

• Number of Taps:
• Increasing the number of taps improves the filter response, resulting in a flatter passband with fewer ripples and reduced ringing.
• A higher tap count also sharpens the attenuation at the cutoff frequency, enhancing the filter's precision.
• However, more taps introduce a larger delay, which may be unsuitable for certain DSP systems.

• Quantization and Filter Coefficient Bit Width:
• Quantization reduces the precision of numbers by mapping them to a fixed set of discrete values, determined by the allocated bit width.
• Using fewer bits for quantization decreases the accuracy of the filter coefficients, negatively impacting the filter's performance.
• Resource Trade-offs:
• There is a trade-off between filter performance and FPGA resource utilization.
• Increasing the number of taps or the bit width of coefficients requires more DSP resources, potentially consuming a significant portion of the FPGA's surface.

By carefully balancing these factors, you can optimize the F-IR filter to meet the specific requirements of your application.

Generating Quantized FIR Filter taps in Matlab

To make the ease of the job, I provided a Matalab code that can easily generate Quantized FIR filter and you can directly use it in Vivado:

close all
clear all
clc
%% setup the parameters here
Sample_Rate = 50e6;
cutoff_frequency = 5e6;
number_of_filter_taps = 191;% must be odd number!
filter_taps_bitwidth = 10;
lowpass_highpass = 'low'; % should be low or high
%% Caluculate the taps
Nyquist_frequency =Sample_Rate/2 ;
Wn = cutoff_frequency/(Nyquist_frequency);
%Generate a row vector b containing the n+1 coefficients 
filter_taps = fir1(number_of_filter_taps-1,Wn,lowpass_highpass);
%% Quantization 
% one bit for sign
filter_taps=floor(filter_taps/max(filter_taps)*(2^(filter_taps_bitwidth-1)-1));
%% plot the filter response
N = 1024; % Number of points for the frequency response
[H, f] = freqz(filter_taps, 1, N, Sample_Rate); % Calculate the frequency response
% Magnitude and phase response
magnitude = abs(H); % Magnitude response

% Plot the filter response
% Magnitude response plot
figure;
plot(f, 20*log10(magnitude),'linewidth',1.3); % Plot magnitude in dB
grid on;
title('Magnitude Response (dB)',FontSize=22);
xlabel_txt = 'Frequency (Hz)';
xlabel(xlabel_txt,FontSize=22);
ylabel('Magnitude (dB)',FontSize=22);
%xlim([0 30e6])
figure
 freqz(filter_taps,1)
figure
stem(filter_taps,'linewidth', 1.3)
grid on;

In the provided Matlab code, you need to configure the following parameters:

• Sample Rate: This is the sampling frequency, which in our design corresponds to the clock frequency driving the system.
• Cutoff Frequency: Specify the cutoff frequency for the filter.
• Number of Taps: Set the number of taps for the filter, which determines the filter's precision and performance.
• Tap Bit Width: Define the bit width for the filter coefficients, which affects the quantization accuracy.
• Filter Type: Select the type of filter you need. This code currently supports only high-pass and low-pass filter designs as simple examples.

FIR Compiler IP Setup in Vivado:

With the help of Matlab code, generate 21 filter taps with cutoff frequency equal to 1MHz and 16bits quantization. A little bit modification is need to make generated values ready to use in Vivado.

• Copy the FIR filter taps and paste them into the Coefficient Vector field under the Filter Options tab.

• Note that as soon as you update the filter coefficients, the output width in the Implementation tab will adjust automatically.
• In the Channel Specification tab, set both the sampling rate and clock frequency to match the clock connected to the FIR filter. For this tutorial, we are using a 100 MHz clock.

• In the Implementation tab, configure the Input Bit Width to match the bit width of your input signal. For example, since the output of the adder in this design has 9 bits, set theinput bit width to 9.

That's it! Your FIR filter is now configured and ready for use.

Please note that the input and output bit widths of the FIR filter are aligned to the correct number of bytes. For example, while we set the input bit width to 9 bits, the filter’s actual input bit width is adjusted to 2 bytes (16 bits).

Now that we’ve confirmed the FIR filter is configured correctly, we can proceed by connecting the output of the adder to the FIR filter input.

Simulation Results

Add a HDL top wrapper to your design and Run the simulation, and you’ll observe that the FIR filter is behaving as a low-pass filter, attenuating the faster signal.

Vivado ImplementationVivado synthesis and implementation.

All the utilized blocks are fully synthesizable, so there’s no need to modify them. However, you must provide a clock source for the design. You can use any clock source, such as the PS-PL clock from the Zinq IP block or an external clock generated using the Clocking Wizard.

If you choose to use the ZYNQ IP block, ensure that the ZYNQ IP is properly initialized; otherwise, the PL side will not receive a clock. For example, you can run a simple "Hello World" program on one of the ARM cores, which will activate the clock for the PL side.

We need to include an ILA in the design to monitor and study the targeted signals. Remove all the extra ports and instead connection them to the ILA.

To keep the process straightforward and avoid using Vitis, I selected to use an external clock available on the ZCU104 board.

Alright, we can now proceed and generate the bitstream.

After running the bitstream on device we should be able to see the same results as simulation!