Extending MicroBlaze Memory Access with Cache and DDR

Introduction

This project walks you through building a complete MicroBlaze-based embedded system on the Xilinx AC701 evaluation board, covering everything from hardware setup to FreeRTOS application development.

• MicroBlaze Configuration Modes: Learn the differences between Microcontroller, Real-Time, and Application Processor presets — and how to choose the right one for your FPGA resources
• Memory Architecture: Understand the integration of local BRAM and external DDR memory using the MIG controller.
• Bus Design: Dive into the Harvard-style memory architecture and how different buses (ILMB, DLMB, AXI) work together.

Using Vivado, you'll configure:

• A MicroBlaze processor with 16KB local BRAM and 8KB instruction/data cache
• AXI interconnects with essential peripherals: AXI Timer, AXI UART (115, 200 baud) and Interrupt Controller
• Clock and reset logic for stable system operation
• DDR memory interface using board files for automatic pin assignment

Finally, you’ll move into the Vitis IDE to:

• Set up a FreeRTOS project
• Build and deploy a Hello World application
• Test UART output and timer functionality

👉Check out the full video

Understanding MicroBlaze Architecture

The figure illustrates MicroBlaze's Harvard Memory Architecture, which uses separate memory systems for instructions (ILMB) and data (DLMB). In this design, ILMB and DLMB buses connect the processor to shared on-chip BRAM through a controller, enabling low-latency, zero wait-state access to local memory within the FPGA.

The MicroBlaze processor supports optional instruction and data caches that connect to external DDR memory via master interfaces, extending its memory access and enabling it to run larger, data-intensive applications beyond the LMB region.

A dedicated Data Peripheral Bus (DPB) connects MicroBlaze to AXI peripherals such as UART and Timer. Additional devices can be added via AXI Interconnect IP.

MicroBlaze supports three configurations:

• Microcontroller: Minimal footprint, no OS

• Real-Time Processor: Moderate peripherals, FreeRTOS support

• Application Processor: Linux-ready, high performance, deeper pipeline

The system architecture includes debug support for tools like Xilinx SDK or Vitis, enabling efficient development, monitoring, and real-time debugging.

Vivado Design

The design targets the AC701 evaluation board in Vivado, where a predefined DDR example is added to the block design. This automatically configures the Memory Interface Generator (MIG) and assigns the approximately 120 required DDR pins using the board files, eliminating the need for manual setup.

A synchronous reset is created using the CPU reset push button and a Processor System Reset block connected to the MIG’s MMCM lock signal.

A MicroBlaze processor is then added with block automation, configured with 16KB of local BRAM and 8KB of cache connected to DDR memory. The debug module is enabled for development purposes, and the processor clock is sourced from the MIG.

Both instruction and data local memory buses (ILMB and DLMB) are enabled to access BRAM, while AXI master ports are activated to connect with DDR memory via the cache.

The AXI peripheral bus is also enabled to allow connection of peripherals like UART and Timer. Adjusting these configuration options impacts the design’s performance and resource usage.

An AXI interconnect is added with two slave ports and one master interface to connect the MicroBlaze cache ports to the DDR memory controller, enabling cache access to external DDR memory.

Another AXI interconnect is added with one master port and three slave ports to link the MicroBlaze peripheral bus with multiple AXI peripherals.

An AXI Timer is included to support the FreeRTOS application, along with an AXI UART configured to 115200 baud.

An AXI Interrupt Controller is connected to the MicroBlaze interrupt port and linked to the second AXI interconnect.

A CONCAT IP is added with two inputs to combine the interrupt signals from the UART and Timer. All IP clock inputs are connected to the MicroBlaze user clock, and reset signals are routed through the Processor System Reset. With the design synchronized and all connections in place, the system is validated.

After validation, the address editor is used to confirm memory and peripheral mapping. A top-level wrapper is created, and for Xilinx evaluation boards, the bitstream is generated and the hardware is exported as an XSA filefor use in a Vitis project.

Due to a known issue in Vitis 2024.1, the FreeRTOS Hello World application doesn't run correctly, so development continues in Vitis 2022.1. A new application project is created using the exported XSA file, with MicroBlaze selected as the processor and FreeRTOS as the operating system.

The Hello World template is chosen to complete the setup. After building and launching the project on the board, the application prints "Hello World, " displays the output time from the AXI Timer, and shows a success message.