Modular 64-Channel EEG System

Why we started this project

Most EEG development platforms are either limited in channel count, difficult to modify, or packaged as closed systems. Our goal is to build the complete acquisition chain ourselves: the low-noise analog front end, digital timing and control, high-throughput transfer, power system, user-facing I/O and mechanical enclosure.

The core design target is **64 simultaneous channels in one module**. A module uses **eight Texas Instruments ADS1299 devices**, with eight channels per converter. The longer-term architecture connects four synchronized modules—one master and three slaves—to reach **256 channels** without redesigning the entire platform.

This is not a single oversized PCB. We deliberately split the system into four boards so that each section can be assembled, debugged and revised independently:

• **Analog Board:** eight ADS1299 front ends, electrode connectors, input protection, reference/bias circuitry and four high-density links to the digital board.
• **Digital EEG Board:** STM32 supervision, an ECP5 FPGA module interface, synchronous sample collection, buffering, Ethernet PHY interface, FTDI FIFO interface and inter-module links.
• **Top Power Board:** protected power entry, power selection and the required regulated supply rails.
• **Top I/O Board:** Ethernet, USB, debug/stream connections, user buttons and status access.

The split-board approach also influenced the enclosure. The 200 mm octagonal Analog Board sits in the bottom half, while the Digital EEG, Top Power and Top I/O boards mount to the lid. When the enclosure is closed, the upper stack mates vertically with the analog section.

System architecture

The intended signal path is:

`Electrodes → protection and channel routing → ADS1299 input multiplexer/PGA → simultaneous 24-bit conversion → DRDY/SPI frames → FPGA → buffering and framing → host interface`

Each ADS1299 handles eight simultaneous channels. Eight converters therefore provide the 64-channel capacity of one Analog Board. The converters are arranged as four two-device groups, and each group has its own high-density connection to the Digital EEG Board. The FPGA is responsible for deterministic acquisition timing and organizing parallel sample streams; the STM32 handles configuration, supervision, board monitoring and communication with the FPGA.

The digital board was designed around an ECP5 FPGA module during development, with the iCESugar Pro used for FPGA bring-up and debugging. The board also includes the physical interfaces required for Ethernet and FT2232H synchronous FIFO experiments. These interfaces are still being validated independently before they are used as the final continuous EEG data path.

The acquisition control sequence is intentionally simple and observable during bring-up:

`initialize → configure → wait for DRDY → capture a complete frame → buffer → transfer`

A detected configuration or capture fault returns the logic to a controlled state instead of allowing partially framed samples into the data stream. This structure gives the STM32 a clear supervisory role while the FPGA handles the timing-sensitive capture path.

Two levels of master/slave organization

The word **master** appears in two different parts of this project, and the distinction matters.

ADS1299 organization inside one Analog Board

One 64-channel Analog Board contains eight ADS1299 devices organized as four two-device groups:

• one master-plus-slave converter pair;
• three slave-plus-slave converter pairs;
• one master and seven slaves in the board-level bias/reference topology.

This arrangement describes the relationship among converters on a single Analog Board. It does not mean that one ADS1299 directly represents the master enclosure.

Master and slave acquisition modules

At system level, each enclosure represents one 64-channel module:

• The **master module** contains the Analog Board, Digital EEG Board, Top Power Board and Top I/O Board.
• A **slave module** contains its own Analog Board and Digital EEG Board, but uses a plain lid and does not duplicate the Top Power or Top I/O boards.
• Vertical stack links carry timing and data between neighbouring modules.
• The first expansion target is one master plus one slave, giving a **128-channel design capacity**.
• The long-term target is one master plus three slaves, giving a **256-channel design capacity**.

The channel counts above describe designed capacity. Multi-module synchronized acquisition has not yet been demonstrated.

Why the ADS1299

The ADS1299 is an eight-channel, simultaneous-sampling, 24-bit delta-sigma analog front end intended for EEG and other biopotential measurements. It combines the converter, programmable gain, input multiplexing, bias-drive support, lead-off functions and internal test facilities in one device. That makes it a strong base for a dense multi-channel board, while still leaving the timing, synchronization, power, PCB layout and data-transport problems to be solved at system level.

Our Analog Board is designed for eight ADS1299 devices, but the first assembly will deliberately start with **one converter**. Power rails, reference nodes, clocking, register readback, internal test signals and known differential inputs will be validated on that single path before the remaining seven devices are populated.

From schematic to physical hardware

The project moved through several parallel workstreams:

1. Four custom PCBs were designed for analog acquisition, digital control, power and front-panel I/O.

2. The digital, power and I/O boards were fabricated and assembled for early board-level testing.

3. STM32-to-FPGA communication was established and the power-board rails were checked.

4. A separate converter test platform was used to develop repeatable acquisition and serial capture tools.

5. A large Altium assembly model was simplified into a manageable mechanical reference.

6. A two-piece enclosure was developed in FreeCAD and repeatedly revised around real boards, connector locations and mounting holes.

The digital stack uses vertical board-to-board connectors rather than loose wiring. This makes the finished module compact, but it also makes mechanical alignment unforgiving: the PCB mounting posts, rectangular stack passages and connector centers must all agree in X, Y and Z.

First PCB bring-up

The first hardware stage focused on the three upper boards before the custom ADS1299 Analog Board was populated. We inspected each PCB individually, powered the stack from a current-limited bench supply and used J-Link plus the iCESugar Pro connection to exercise the STM32 and FPGA paths.

The early photographs also preserve the state of the individual fabricated boards before they were assembled into the vertical stack:

The initial checks established power and reset progress and confirmed that the STM32 and FPGA could communicate. During debugging, a short involving two pins was found and corrected. Measurements near 1.2 V for the FPGA core domain and 3.3 V for the I/O domain were recorded, together with an active PHY reset level. These checks did not prove Ethernet packet transfer, so Ethernet remains a separate validation milestone.

Building the enclosure from imperfect mechanical data

The original Altium STEP assembly was approximately 123 MB and contained a large amount of geometry that was irrelevant to an enclosure: individual resistors, capacitors, IC bodies and other small components. We generated a lightweight mechanical reference that retained the PCB outlines, important connectors, mounting holes and conservative component-height envelopes.

The resulting enclosure is a two-piece octagonal FDM design measuring approximately **221 × 221 × 61.5 mm**:

• The **bottom half** carries the octagonal Analog Board.
• The **lid** carries the Digital EEG Board, Top Power Board and Top I/O Board.
• Eight radial openings provide access to the Analog Board's DB25-PL-24 connectors.
• Two rectangular passages align with the Analog Board's central stack data/power openings.
• Eight dedicated analog-board posts align with the holes in the latest bare-board STEP model.
• Four separate case screws close the two enclosure halves.
• Vent slots, recessed labels, a circuit-brain logo and rounded exterior details were added without changing the connector interfaces.

The large footprint is intentional: the Analog Board is approximately 200 mm across and distributes eight DB25 connectors around its perimeter. A Bambu Lab-size 256 mm build plate can accommodate each 221 mm enclosure half individually.

The first printed lid—and what it taught us

The first printed lid confirmed that the overall octagonal form, raised I/O region, ventilation, engraved labels and board pockets could be manufactured as one FDM part. It also gave us the first real view of the interface hierarchy: analog connectors around the bottom, upper electronics in the lid, and Ethernet/USB/buttons presented on the raised top surface.

The physical stack also revealed that the approximate STEP assembly did not represent the underside connector position of the latest Top I/O Board. The entire I/O board could not be corrected by moving only the Ethernet opening; the PCB, its mounting posts, USB connectors, buttons, raised chamber, labels and access wells all had to move together.

Using the real board photograph and its 50 × 50 mm outline as a scale reference, the latest CAD revision translates the complete Top I/O assembly approximately **11.38 mm outward** and **0.35 mm laterally** so that its underside connector aligns with the Digital EEG Board connector. Because this correction was derived from an image, it remains a fit-check revision until it is confirmed with a direct measurement or an updated production STEP model.

This is exactly why we are treating the enclosure as an engineering prototype rather than decoration added at the end. Every print feeds real information back into the PCB-stack model.

Current test platform

Alongside the custom boards, we developed a separate converter test setup for firmware and measurement workflow. The original ADS1299 test device failed, so current repeatable bench acquisition uses an ADS1296. This is useful for exercising SPI transactions, data-ready timing, framed serial transport, CSV capture and signal-analysis tooling, but it is not being presented as final ADS1299 performance.

The ADS1296 board connects to an STM32 NUCLEO-H7A3ZI-Q. A 47 kΩ/49.9 Ω divider reduces the function-generator signal to the microvolt range at the converter input. Current controlled captures use a 2.048 MHz external clock, a 2 kSPS data rate and the ADS1296 internal 4 V reference. Tests include internally shorted channels and known differential sine inputs, including 5 Hz, 10 Hz and 40 Hz cases. The saved captures retain channel, sample sequence, converter status, gain, reference, raw code and calculated input voltage.

The current diagnostic firmware can:

• start the converter with a controlled power-up sequence;
• verify device identity and configuration register readback;
• capture data-ready events and uninterrupted sample frames;
• select and label channels and input modes;
• stream framed samples with sequence numbers, timestamps, status and CRC;
• save decoded captures for time-domain and spectral analysis.

The firmware sends 41-byte host packets containing a header, packet type, sequence number, millisecond timestamp, input mode, active channel, three status bytes, six signed 24-bit channel words, capture flags, CRC-16 and a footer. This outer serial packet should not be confused with the converter’s raw SPI frame. The ADS1296 produces a 21-byte converter frame for six channels, while the target ADS1299 uses a 27-byte frame for eight channels.

An earlier diagnostic run at 500 SPS and gain-1 scaling showed a large 49–50 Hz component in the normal-input capture. The internally shorted capture was much smaller. Those plots helped expose pickup and test-fixture limitations, but they are not a final noise result. The newer 2 kSPS captures use improved labeling, longer records and known-input metadata so that the ADS1299 tests can later follow the same repeatable procedure.

ADS1299-specific configuration, scaling and noise measurements will be repeated on the custom Analog Board after the first device is assembled.

What has been demonstrated

• The Digital EEG, Top Power and Top I/O PCBs have been fabricated.
• Board-level power and reset checks have been performed on the digital stack.
• STM32-to-FPGA communication has been exercised.
• FPGA synthesis, place-and-route and bitstream generation have completed successfully for diagnostic logic.
• A structured ADC capture pipeline has been implemented on the separate ADS1296 test setup.
• A two-piece enclosure has been designed and exported as FreeCAD, STEP and STL files.
• The first large-format lid/enclosure fit-check has been printed.
• The analog-board holes, DB25 access, central stack passages and upper-board mounting features have been incorporated into later enclosure revisions.

## What is still in progress

• Assemble and validate the first ADS1299 path on the custom Analog Board.
• Confirm all ADS1299 registers, reference voltages, clocking and input scaling.
• Expand from one validated converter to all eight devices and 64 channels.
• Complete repeatable Ethernet PHY identification, link and packet tests.
• Validate FT2232H FIFO payload transfer with the host interface configured.
• Print and physically verify the corrected I/O-board lid revision.
• Demonstrate synchronization between one master and one slave module before attempting the four-module target.
• Develop reliable live visualization and recording software for synchronized channel data.

The system is currently an engineering and educational prototype tested with internal/known test signals and controlled bench inputs. It is not a medical device.

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# Development timeline

## 20 July 2026 — Complete electronics assembly modeled

The first complete 3D assembly established the project’s mechanical direction before an enclosure existed. The octagonal Analog Board carried eight radial DB25 interfaces, while the Digital EEG, Top Power and Top I/O boards formed a vertical stack above it. Exploded views exposed the connector relationships that later drove the two-piece enclosure architecture.

## 24 July 2026 — Analog design revision captured

The retained Analog Board schematic was finalized as design revision DES-A. It defines the eight-ADS1299, 64-channel front end, four two-device groups, protection network, bias/reference arrangement and interfaces to the Digital EEG Board.

## 26 August 2026 — First digital and power hardware bring-up

The fabricated digital-control and power PCBs arrived. The power section was checked and the STM32-to-FPGA link was exercised successfully. The project was still waiting for some board-to-board connectors, so the full multi-board stack could not yet be tested. The decision was made to assemble the Analog Board progressively: one ADS1299 first, followed by the remaining seven only after the first signal path is repeatable.

The individual Digital EEG, Top Power and Top I/O photographs in the gallery document this first bring-up stage. They also preserve the original component population and the user-interface orientation before later enclosure corrections.

## 8 September 2026 — Upper digital stack assembled

The Digital EEG, Top Power and Top I/O boards were assembled into the first practical upper stack. Bench work used a current-limited supply and J-Link connection to inspect rails, resets and the STM32/FPGA communication path. The Ethernet connector and PHY were present, but no completed cable-and-packet test was recorded, so the work remained board-level bring-up rather than a demonstrated network stream.

## 12–13 September 2026 — Mechanical model cleanup and enclosure architecture

The large Altium assembly STEP was imported and reduced to the geometry needed for mechanical design. Small passives and detailed IC packages were removed from the working reference, while board outlines, connector bodies, mounting holes and clearance envelopes were retained.

The first complete enclosure architecture was then generated in FreeCAD: octagonal bottom for the Analog Board, board-carrying lid for the digital/power/I/O stack, eight DB25 openings, central stack passages, ventilation and case fasteners. Separate printable STL and editable STEP/FreeCAD outputs were generated for the top and bottom halves.

## 13 September 2026 — Mounting, access and appearance revisions

The Analog Board's two central rectangular connector slots were transferred into matching through-openings in the enclosure bottom. Case screw passages were corrected so the locating rim did not obstruct their pilot entrances. The supplied circuit-brain graphic was traced into a recessed lid engraving, and interface labels were added for Ethernet, buttons, USB, debug, stream and power. Rounded edges and shallow exterior fillets improved the printed appearance without changing the PCB interfaces.

## 14 September 2026 — Master/slave enclosure architecture documented

The enclosure work expanded from one master unit to a modular family. The master retained all four boards and its raised user-interface lid. The slave design retained the Analog and Digital EEG boards but replaced the upper I/O hardware with a plain lid containing the required vertical stack passages. CAD views documented one-master/one-slave packaging as the first expansion step and one-master/three-slave packaging as the 256-channel target.

## 15 September 2026 — Repeatable converter capture workflow

The separate ADS1296 bench platform was used to validate the acquisition workflow: controlled startup, register readback, 2 kSPS framed sample capture, channel labeling, CRC-protected serial packets and CSV decoding. Known generator inputs and internally shorted inputs were recorded for analysis. These results validate the test method and software path, not the final ADS1299 board.

## 16 September 2026 — ADS1296 known-input bench testing

The converter test board was connected to an STM32 NUCLEO, laboratory function generator and oscilloscope. A resistor divider reduced the source amplitude to a microvolt-level differential input. The setup produced longer labeled captures suitable for time-domain checks, power-spectral-density analysis and 50 Hz interference comparison. The same measurement discipline will be applied to the custom ADS1299 board.

## 16 September 2026 — Latest analog mounting reference and I/O correction

A newer bare Analog Board STEP supplied the actual eight mounting holes. The bottom enclosure was revised to use eight aligned screw posts instead of edge clamps, including the board's intentionally asymmetric hole position.

The Top I/O Board was also corrected after its real underside connector became visible. The entire board assembly was shifted together in CAD so the board-to-board connector aligns with the digital stack. The revised top and unchanged bottom passed solid, mesh and modeled-clearance checks, but the image-derived I/O shift still needs a physical fit confirmation.

## 19 September 2026 — First enclosure print documented

The first large enclosure/lid revision was assembled with the existing upper PCBs for a practical fit-check. The print demonstrates the overall physical scale, board pockets, raised interface panel, vents, labels and logo. It also documents the pre-correction I/O arrangement and therefore serves as a visible development milestone rather than the final enclosure.