Adam Taylor
Published © GPL3+

So you want to Design a FPGA IP Core!

Developing and Verifying a FPGA IP block requires a lot more thought than just writing the HDL. Lets take a look at how to do it!

BeginnerFull instructions provided5 hours6,543
So you want to Design a FPGA IP Core!

Things used in this project

Hardware components

ZUBoard 1CG
Avnet ZUBoard 1CG
×1

Software apps and online services

Vivado Design Suite
AMD Vivado Design Suite

Story

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Schematics

Complete Vivado Project

Vivado 2023.1

Credits

Adam Taylor

Adam Taylor

129 projects • 2222 followers
Adam Taylor is an expert in design and development of embedded systems and FPGA’s for several end applications (Space, Defense, Automotive)

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