Does Your FPGA Work? Let It Tell You

Introduction

One of the things that is often overlooked when you develop a new board is a production test application. This application should test the board and its interfaces to demonstrate if the board is functional or indicate areas where the design is not functional.

In the context of production, this can be used as the go/no-go for the board. If it passes, then it can be shipped to the user.

This application can also be used in the field if a user raises questions or worries about the board's functionality. The user can be asked to load it on and run through the checks and indicate if there are any issues or not.

This test needs to be well architected. In this example, we are going to use the AMD Spartan™ 7 FPGA as an example of a new production board and demonstrate how we can create a self-test application.

This application will test the following:

• Slider switches
• Push button switches
• 4 LEDs
• 2 RGB LEDs
• Four Pmod connectors
• DDR3 memory
• Serial interface

This approach will use software to test all of these interfaces. However, how we run the software is something we need to understand and think about carefully. We want to test the main clock, which means we will be running the AMD MicroBlaze™ V processors from the FPGA configuration clock.

Architecture

The architecture of the test system is critical. For example, we cannot be sure the oscillator on the board to the FPGA is correctly functioning. Therefore, the MicroBlaze™ V will run from the internal configuration clock of the FPGA. This allows the MicroBlaze™ V to check switches and interfaces without the need to use a serial port if necessary. This can be achieved by communication via the LEDs (e.g., flashing LEDs in specific patterns to indicate a specific test).

Of course, the internal configuration clock frequency depends on the Process, Variation, and Temperature. As such, its frequency, while a nominal 100MHz in the Spartan™-7 series, is likely to vary considerably, making it unsuitable for DDR3 reference clocks or even UART timing references.

To aid visual debugging of the system, one of the LEDs shall be used to indicate to the user that the main clock oscillator is present and locked.

When locked, LED 0 on the board will illuminate. This gives confidence that the remainder of the test application can be run using the serial port commands.

To test the connections, we will drive signals out of the JA / JB Pmod™ connectors and receive them on the JC / JD Pmod™ connectors. We will also make sure the push button switches and slide switches toggle.

The DDR3 will be tested while the XADC™ (Xilinx Analog-to-Digital Converter) will be used to make sure voltages and temperatures are within acceptable limits before testing starts.

FPGA Design

The first thing we need to do is create a new AMD Vivado™ Design Suite design to define the contents of the FPGA.

Create a new project, targeting the Digilent Arty S7-50 board.

Once the project is open, create a new block diagram.

Add the DDR3 memory to the IP Integrator™ diagram.

Delete the clock ports, which will appear on the DDR port.

We need to make some changes to the DDR configuration. The first change is to set the input clock period to 200 MHz.

Change the reference clock, which is 200 MHz, to use the system clock.

Close the DDR wizard and add a new clocking wizard.

Set the output clock to 200 MHz and remove the reset input.

Close the clocking wizard, and connect as shown below in the IP Integrator design.

To manage the reset, we need to add a processor system reset block. Connect the reset input to the red reset button on the Arty board. Connect the locked and clock out signals to the reset block. Then, connect the reset outputs to the Memory Interface Generator (MIG).

Add a MicroBlaze V Processor to the design.

Run the block automation, and leave the clock connection set to “None”.

This will create the design elements shown below.

The next step is to create the clock source from the configuration clock. We need to use RTL to do this—create a new design source.

Create a new RTL source file.

Click “Finish” to add the file.

If the define module window pops up, click “Cancel”, then click “Yes” if asked for confirmation.

Open the created file in the editor, and copy and paste in the code below. This code accesses the configuration clock using the STARTUPE2 primitive, and then buffers it using a global buffer (BUFG).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity int_ext_clk is
Port (
	   clk_op  : out std_logic
     );
end int_ext_clk; 

architecture Behavioral of int_ext_clk is
    
    signal s_cclk         : std_ulogic;
    
begin
 STARTUPE2_inst : STARTUPE2
   generic map (
      PROG_USR => "FALSE",  
      SIM_CCLK_FREQ => 10.0  
   )
   port map (
      CFGCLK => open,      
      CFGMCLK => s_cclk,    
      EOS => open,          
      PREQ => open,       
      CLK => '0',           
      GSR => '0',             
      GTS => '0',           
      KEYCLEARB => '0',   
      PACK => '0',         
      USRCCLKO => '0',               
      USRCCLKTS => '0',                         
	  USRDONEO => '1',   -- 1-bit input: User DONE pin output control
      USRDONETS => '1'  -- 1-bit input: User DONE 3-state enable outpu
);

   BUFG_inst : BUFG
   port map (
      O => clk_op, -- 1-bit output: Clock output
      I => s_cclk  -- 1-bit input: Clock input
   );


end Behavioral;

To use the file just created, go to the IP Integrator, and drag and drop the module onto the block diagram.

Connect this clock to the MicroBlaze V processor, clocking both the core and its BRAM memories.

To communicate with other peripherals over AXI, we need to add an AXI Interconnect. Ensure the clocks and resets are correctly connected, and use the startup clock as the source.

Connect S00_AXI as shown below.

Drag and drop the following peripherals from the Boards tab, and connect them to the AXI Interconnect. For the DDR, ensure the clock is the UI Clock. For all other elements, use the 200 MHz clock from the oscillator.

• 2 RGB LEDS
• 4 Push Buttons
• 4 Switches
• USB UART

Also add two AXI GPIO blocks, both configured for 16 bits—one set as output, and the other as input. Connect the output GPIO to JA and JB, and the input GPIO to JC and JD. This setup allows us to drive signals from one GPIO and receive them on the second. If a signal fails to toggle, we know there’s an issue.

The final project should look as shown below. The complete design is available on my GitHub.

To build the target, we also need to add constraints, which are:

set_property PACKAGE_PIN C18 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets self_test_i/clk_wiz_0/inst/clk_in1_self_test_clk_wiz_0_0]
set_property IOSTANDARD LVCMOS33 [get_ports CLOCK_TEST]

set_property IOSTANDARD SSTL135 [get_ports {dip_switches_4bits_tri_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switches_4bits_tri_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switches_4bits_tri_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dip_switches_4bits_tri_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JAJB_tri_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JCJD_tri_i[0]}]
set_property PACKAGE_PIN L17 [get_ports {JAJB_tri_o[0]}]
set_property PACKAGE_PIN L18 [get_ports {JAJB_tri_o[1]}]
set_property PACKAGE_PIN M14 [get_ports {JAJB_tri_o[2]}]
set_property PACKAGE_PIN N14 [get_ports {JAJB_tri_o[3]}]
set_property PACKAGE_PIN M16 [get_ports {JAJB_tri_o[4]}]
set_property PACKAGE_PIN M17 [get_ports {JAJB_tri_o[5]}]
set_property PACKAGE_PIN M18 [get_ports {JAJB_tri_o[6]}]
set_property PACKAGE_PIN N18 [get_ports {JAJB_tri_o[7]}]
set_property PACKAGE_PIN P16 [get_ports {JAJB_tri_o[8]}]
set_property PACKAGE_PIN N15 [get_ports {JAJB_tri_o[9]}]
set_property PACKAGE_PIN P15 [get_ports {JAJB_tri_o[10]}]
set_property PACKAGE_PIN P14 [get_ports {JAJB_tri_o[11]}]
set_property PACKAGE_PIN T18 [get_ports {JAJB_tri_o[12]}]
set_property PACKAGE_PIN R18 [get_ports {JAJB_tri_o[13]}]
set_property PACKAGE_PIN P18 [get_ports {JAJB_tri_o[14]}]
set_property PACKAGE_PIN P17 [get_ports {JAJB_tri_o[15]}]
set_property PACKAGE_PIN V14 [get_ports {JCJD_tri_i[0]}]
set_property PACKAGE_PIN R13 [get_ports {JCJD_tri_i[1]}]
set_property PACKAGE_PIN P13 [get_ports {JCJD_tri_i[2]}]
set_property PACKAGE_PIN U16 [get_ports {JCJD_tri_i[3]}]
set_property PACKAGE_PIN U18 [get_ports {JCJD_tri_i[4]}]
set_property PACKAGE_PIN U17 [get_ports {JCJD_tri_i[5]}]
set_property PACKAGE_PIN V16 [get_ports {JCJD_tri_i[6]}]
set_property PACKAGE_PIN U15 [get_ports {JCJD_tri_i[7]}]
set_property PACKAGE_PIN U11 [get_ports {JCJD_tri_i[8]}]
set_property PACKAGE_PIN T11 [get_ports {JCJD_tri_i[9]}]
set_property PACKAGE_PIN R11 [get_ports {JCJD_tri_i[10]}]
set_property PACKAGE_PIN T13 [get_ports {JCJD_tri_i[11]}]
set_property PACKAGE_PIN T12 [get_ports {JCJD_tri_i[12]}]
set_property PACKAGE_PIN V13 [get_ports {JCJD_tri_i[13]}]
set_property PACKAGE_PIN U12 [get_ports {JCJD_tri_i[14]}]
set_property PACKAGE_PIN V15 [get_ports {JCJD_tri_i[15]}]

set_property PACKAGE_PIN L13 [get_ports CLOCK_TEST]

set_property IOSTANDARD LVCMOS33 [get_ports {led_4bits_tri_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_4bits_tri_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_4bits_tri_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk_led]
set_property PACKAGE_PIN F13 [get_ports {led_4bits_tri_o[0]}]
set_property PACKAGE_PIN E13 [get_ports {led_4bits_tri_o[1]}]
set_property PACKAGE_PIN H15 [get_ports {led_4bits_tri_o[2]}]
set_property PACKAGE_PIN E18 [get_ports clk_led]

Software Development

The software is developed in the AMD Vitis™ Unified Software Platform, and it lies at the heart of the self-test capabilities.

This application software needs to be able to test interfaces, switches, and the DDR Memory.

To keep the self-test application expandable and maintainable, the software is split into several functions.

ReadSystemMonitorValues()

Reads temperature and voltage values from the XADC. Converts raw ADC values to real-world units and prints them. Also checks if the values are within acceptable limits and returns an error flag if any are out of range.

TestPushButtons()

Iteratively checks each push button by prompting the user to press and release it. Tracks state changes to detect failures and returns a bitmask indicating which buttons (if any) failed.

TestSliderSwitches()Similar to the button test, but for slider switches. It prompts the user to toggle each switch and checks for correct behavior in both directions. Returns a bitmask of failed switches.

TestIOPins()Tests connectivity between output and input GPIO pins. Prompts the user to make physical connections, then toggles outputs and verifies inputs respond as expected. Flags any failed pins in a bitmask.

TestDDRMemory()Performs multiple memory tests on DDR RAM:

Address test: writes address values as data.

Walking ones test: writes/reads bit patterns.

Alternating patterns test: verifies values like 0xA5A5 and 0x5A5A.Returns 0 if all tests pass or 1 if any errors are detected.

DisplayTestSummary(int failed_buttons, int failed_switches, int failed_pins, int memory_failed)

Consolidates the results of all tests. Reports which buttons, switches, and I/O pins (if any) failed, and whether the DDR memory passed. Outputs a summary message indicating whether all tests passed or some failed.

The complete code can be seen below. It is also available on the GitHub repository.

#include <stdio.h>
#include <stdlib.h> // For abs() function
#include "platform.h"
#include "xil_printf.h"
#include "xgpio.h"
#include "xparameters.h"
#include "sleep.h"
#include "xsysmon.h"
// Define GPIO device IDs
#define GPIO_DEVICE_ID XPAR_AXI_GPIO_2_BASEADDR
#define PB_GPIO_DEVICE_ID XPAR_XGPIO_0_BASEADDR
#define SW_GPIO_DEVICE_ID XPAR_AXI_GPIO_1_BASEADDR
// Channel definitions
#define OUTPUT_CHANNEL 1 // Channel 1 for outputs
#define INPUT_CHANNEL  2 // Channel 2 for inputs
#define PB_CHANNEL     2 // Push button channel
#define SW_CHANNEL     1 // Slider switch channel
// Number of pins to test
#define NUM_PINS 16
#define NUM_BUTTONS 4
#define NUM_SWITCHES 4
// System Monitor device ID with your actual XADC ID
#define SYSMON_DEVICE_ID XPAR_XADC_WIZ_0_BASEADDR
// Voltage ranges for Spartan-7 devices (in Volts)
// These are the nominal values ±5% as per Xilinx documentation
#define VCCINT_MIN  0.95 // Nominal is 1.0V
#define VCCINT_MAX  1.05
#define VCCAUX_MIN  1.71 // Nominal is 1.8V
#define VCCAUX_MAX  1.89
#define VCCBRAM_MIN 0.95 // Nominal is 1.0V
#define VCCBRAM_MAX 1.05
// Temperature limits (in degrees Celsius)
#define TEMP_WARNING 85.0
#define TEMP_CRITICAL 100.0
// DDR Memory Test Parameters
#define DDR_BASE_ADDR 0x80000000 // Base address of DDR memory
#define DDR_SIZE      0x10000000 // 256MB memory size
#define DDR_WIDTH     16 // 16-bit width
// Global System Monitor instance
XSysMon SysMonInst;
// Global GPIO instances
XGpio gpio;
XGpio pb_gpio;
XGpio sw_gpio;
// Function prototypes
int InitializePlatform(void);
int ReadSystemMonitorValues(void);
int CheckVoltages(float vccint, float vccaux, float vccbram);
int xil_printf_float(float x);
int TestPushButtons(void);
int TestSliderSwitches(void);
int TestIOPins(void);
int TestDDRMemory(void);
void DisplayTestSummary(int failed_buttons, int failed_switches, int failed_pins, int memory_failed);
int main()
{
int status;
int failed_buttons = 0;
int failed_switches = 0;
int failed_pins = 0;
int memory_failed = 0;
int voltage_error = 0;
// Initialize the platform and all peripherals
status = InitializePlatform();
if (status != XST_SUCCESS) {
xil_printf("Platform initialization failed! Test aborted.\r\n");
return XST_FAILURE;
}
// Read System Monitor values at the beginning and check for errors
voltage_error = ReadSystemMonitorValues();
if (voltage_error) {
xil_printf("\r\n!!! WARNING: Voltage readings outside of acceptable range for Spartan-7 !!!\r\n");
xil_printf("Do you want to continue with the test? (y/n): ");
char response = getchar();
if (response != 'y' && response != 'Y') {
xil_printf("\r\nTest aborted due to voltage issues.\r\n");
cleanup_platform();
return XST_FAILURE;
}
xil_printf("\r\nContinuing test despite voltage issues...\r\n\r\n");
}
// Run all tests
xil_printf("\r\n");
xil_printf("STARTING SYSTEM TESTS\r\n");
xil_printf("====================\r\n");
// Test push buttons
failed_buttons = TestPushButtons();
// Test slider switches
failed_switches = TestSliderSwitches();
// Test I/O pins
failed_pins = TestIOPins();
// Test DDR memory
memory_failed = TestDDRMemory();
// Display test summary
DisplayTestSummary(failed_buttons, failed_switches, failed_pins, memory_failed);
// Final System Monitor readings
xil_printf("\r\nFinal System Readings:\r\n");
voltage_error = ReadSystemMonitorValues();
if (voltage_error) {
xil_printf("\r\n!!! WARNING: Final voltage readings outside of acceptable range for Spartan-7 !!!\r\n");
}
xil_printf("\r\nTest complete. Press any key to exit...\r\n");
getchar();
// Clean up
cleanup_platform();
return 0;
}
// Initialize platform and peripherals
int InitializePlatform(void)
{
int status;
// Initialize platform
init_platform();
xil_printf("\r\n\r\n");
xil_printf("GPIO Connectivity Test Application\r\n");
xil_printf("================================\r\n\r\n");
// Initialize System Monitor
XSysMon_Config *ConfigPtr;
ConfigPtr = XSysMon_LookupConfig(SYSMON_DEVICE_ID);
if (ConfigPtr == NULL) {
xil_printf("System Monitor Lookup Config Failed\r\n");
return XST_FAILURE;
}
status = XSysMon_CfgInitialize(&SysMonInst, ConfigPtr, ConfigPtr->BaseAddress);
if (status != XST_SUCCESS) {
xil_printf("System Monitor Initialization Failed\r\n");
return XST_FAILURE;
}
// Initialize the GPIO driver for main I/O
status = XGpio_Initialize(&gpio, GPIO_DEVICE_ID);
if (status != XST_SUCCESS) {
xil_printf("GPIO Initialization Failed\r\n");
return XST_FAILURE;
}
// Initialize the GPIO driver for push buttons
status = XGpio_Initialize(&pb_gpio, PB_GPIO_DEVICE_ID);
if (status != XST_SUCCESS) {
xil_printf("Push Button GPIO Initialization Failed\r\n");
return XST_FAILURE;
}
// Initialize the GPIO driver for slider switches
status = XGpio_Initialize(&sw_gpio, SW_GPIO_DEVICE_ID);
if (status != XST_SUCCESS) {
xil_printf("Slider Switch GPIO Initialization Failed\r\n");
return XST_FAILURE;
}
// Set channel 1 as output and channel 2 as input on main GPIO
XGpio_SetDataDirection(&gpio, OUTPUT_CHANNEL, 0x0000);  // All outputs (0 = output)
XGpio_SetDataDirection(&gpio, INPUT_CHANNEL, 0xFFFF);   // All inputs (1 = input)
// Set push button channel as input
XGpio_SetDataDirection(&pb_gpio, PB_CHANNEL, 0xFFFF);   // All inputs (1 = input)
// Set slider switch channel as input
XGpio_SetDataDirection(&sw_gpio, SW_CHANNEL, 0xFFFF);   // All inputs (1 = input)
// Configure the System Monitor/XADC
// Set the configuration registers for proper operation
XSysMon_SetSequencerMode(&SysMonInst, XSM_SEQ_MODE_SAFE);
// Enable the channels we want to monitor (temperature and voltages)
XSysMon_SetSequencerMode(&SysMonInst, XSM_SEQ_MODE_CONTINPASS);
// Wait for the configuration to take effect
usleep(500000); // 500ms delay
return XST_SUCCESS;
}
// Function to test push buttons
// Returns a bitmask of failed buttons (0 = all passed)
int TestPushButtons(void)
{
u32 initial_state;
u32 pressed_state;
u32 released_state;
u32 button_mask;
int failed_buttons = 0;
xil_printf("\r\n");
xil_printf("PUSH BUTTON TEST\r\n");
xil_printf("===============\r\n\r\n");
for (int btn = 0; btn < NUM_BUTTONS; btn++) {
button_mask = (1 << btn);
// Read initial state of buttons
initial_state = XGpio_DiscreteRead(&pb_gpio, PB_CHANNEL) & button_mask;
xil_printf("TEST BUTTON %d:\r\n", btn + 1);
xil_printf("Please press and hold Button %d...\r\n", btn + 1);
// Wait for button press (with timeout)
int timeout_count = 0;
int state_changed = 0;
while (timeout_count < 50 && !state_changed) {
pressed_state = XGpio_DiscreteRead(&pb_gpio, PB_CHANNEL) & button_mask;
// Check if state changed from initial state
if (pressed_state != initial_state) {
state_changed = 1;
}
usleep(100000);  // 100ms delay
timeout_count++;
}
if (!state_changed) {
xil_printf("ERROR: Button %d did not change state when pressed\r\n", btn + 1);
failed_buttons |= button_mask;
continue;
}
xil_printf("Button %d press detected. Please release Button %d...\r\n", btn + 1, btn + 1);
// Wait for button release (with timeout)
timeout_count = 0;
state_changed = 0;
while (timeout_count < 50 && !state_changed) {
released_state = XGpio_DiscreteRead(&pb_gpio, PB_CHANNEL) & button_mask;
// Check if state changed back to initial state
if (released_state == initial_state) {
state_changed = 1;
}
usleep(100000);  // 100ms delay
timeout_count++;
}
if (!state_changed) {
xil_printf("ERROR: Button %d did not return to initial state when released\r\n", btn + 1);
failed_buttons |= button_mask;
continue;
}
xil_printf("Button %d test PASSED\r\n\r\n", btn + 1);
}
return failed_buttons;
}
// Function to test slider switches
// Returns a bitmask of failed switches (0 = all passed)
int TestSliderSwitches(void)
{
u32 initial_state;
u32 toggled_state;
u32 switch_mask;
int failed_switches = 0;
xil_printf("\r\n");
xil_printf("SLIDER SWITCH TEST\r\n");
xil_printf("=================\r\n\r\n");
for (int sw = 0; sw < NUM_SWITCHES; sw++) {
switch_mask = (1 << sw);
// Read initial state of switch
initial_state = XGpio_DiscreteRead(&sw_gpio, SW_CHANNEL) & switch_mask;
xil_printf("TEST SWITCH %d:\r\n", sw + 1);
if (initial_state) {
xil_printf("Switch %d is currently ON. Please slide it to OFF position...\r\n", sw + 1);
} else {
xil_printf("Switch %d is currently OFF. Please slide it to ON position...\r\n", sw + 1);
}
// Wait for switch toggle (with timeout)
int timeout_count = 0;
int state_changed = 0;
while (timeout_count < 50 && !state_changed) {
toggled_state = XGpio_DiscreteRead(&sw_gpio, SW_CHANNEL) & switch_mask;
// Check if state changed from initial state
if (toggled_state != initial_state) {
state_changed = 1;
}
usleep(100000);  // 100ms delay
timeout_count++;
}
if (!state_changed) {
xil_printf("ERROR: Switch %d did not change state when toggled\r\n", sw + 1);
failed_switches |= switch_mask;
continue;
}
// Now toggle switch back
if (toggled_state) {
xil_printf("Switch %d toggled to ON. Please slide it back to OFF position...\r\n", sw + 1);
} else {
xil_printf("Switch %d toggled to OFF. Please slide it back to ON position...\r\n", sw + 1);
}
// Wait for switch toggle back (with timeout)
timeout_count = 0;
state_changed = 0;
while (timeout_count < 50 && !state_changed) {
toggled_state = XGpio_DiscreteRead(&sw_gpio, SW_CHANNEL) & switch_mask;
// Check if state changed back to initial state
if (toggled_state == initial_state) {
state_changed = 1;
}
usleep(100000);  // 100ms delay
timeout_count++;
}
if (!state_changed) {
xil_printf("ERROR: Switch %d did not change back to original state when toggled\r\n", sw + 1);
failed_switches |= switch_mask;
continue;
}
xil_printf("Switch %d test PASSED\r\n\r\n", sw + 1);
}
return failed_switches;
}
// Function to test I/O pin connectivity
// Returns a bitmask of failed pins (0 = all passed)
int TestIOPins(void)
{
u32 input_value;
u32 pin_mask;
int failed_pins = 0;
xil_printf("\r\n");
xil_printf("I/O PIN CONNECTIVITY TEST\r\n");
xil_printf("======================\r\n\r\n");
// First, set all outputs to 0
XGpio_DiscreteWrite(&gpio, OUTPUT_CHANNEL, 0x0000);
// Test each pin connection one by one
for (int pin = 0; pin < NUM_PINS; pin++) {
pin_mask = (1 << pin);
xil_printf("TEST PIN %d:\r\n", pin + 1);
xil_printf("Please connect output %d to input %d...\r\n", pin + 1, pin + 1);
xil_printf("Press any key to continue...\r\n");
getchar();  // Wait for user input
// Test LOW to HIGH transition
xil_printf("Testing LOW to HIGH transition...\r\n");
// Set output pin LOW
XGpio_DiscreteWrite(&gpio, OUTPUT_CHANNEL, 0x0000);
usleep(10000);  // Short delay
// Read input pin (should be LOW)
input_value = XGpio_DiscreteRead(&gpio, INPUT_CHANNEL) & pin_mask;
if (input_value != 0) {
xil_printf("ERROR: Input pin %d is HIGH when output is LOW\r\n", pin + 1);
failed_pins |= pin_mask;
continue;  // Move to next pin
}
// Set output pin HIGH
XGpio_DiscreteWrite(&gpio, OUTPUT_CHANNEL, pin_mask);
usleep(10000);  // Short delay
// Read input pin (should be HIGH)
input_value = XGpio_DiscreteRead(&gpio, INPUT_CHANNEL) & pin_mask;
if (input_value == 0) {
xil_printf("ERROR: Input pin %d is LOW when output is HIGH\r\n", pin + 1);
failed_pins |= pin_mask;
continue;  // Move to next pin
}
// Test HIGH to LOW transition
xil_printf("Testing HIGH to LOW transition...\r\n");
// Set output pin LOW again
XGpio_DiscreteWrite(&gpio, OUTPUT_CHANNEL, 0x0000);
usleep(10000);  // Short delay
// Read input pin (should be LOW again)
input_value = XGpio_DiscreteRead(&gpio, INPUT_CHANNEL) & pin_mask;
if (input_value != 0) {
xil_printf("ERROR: Input pin %d is HIGH when output is LOW\r\n", pin + 1);
failed_pins |= pin_mask;
continue;  // Move to next pin
}
xil_printf("Pin %d connectivity test PASSED\r\n\r\n", pin + 1);
// Read System Monitor values after each pin test
if (pin % 4 == 0) {  // Read every 4 pins to reduce output clutter
int voltage_error = ReadSystemMonitorValues();
if (voltage_error) {
xil_printf("\r\n!!! WARNING: Voltage readings outside of acceptable range for Spartan-7 !!!\r\n\r\n");
}
}
}
return failed_pins;
}
// Function to test DDR memory
int TestDDRMemory(void)
{
volatile u16 *ddr_ptr = (volatile u16 *)DDR_BASE_ADDR;
u32 errors = 0;
u32 address_errors = 0;
u32 data_errors = 0;
u32 total_locations = DDR_SIZE / sizeof(u16);
u32 test_pattern;
u32 read_value;
u32 expected_value;
xil_printf("\r\n");
xil_printf("DDR MEMORY TEST\r\n");
xil_printf("==============\r\n");
xil_printf("\r\nDDR Memory Test (256MB @ 0x%08x):\r\n", DDR_BASE_ADDR);
xil_printf("--------------------------------------\r\n");
// Address test (write address as data)
xil_printf("Running address test (writing address values)...\r\n");
// Write phase - write memory address to each location
for (u32 i = 0; i < total_locations; i += 1024) {
// Show progress every 16MB
if (i % (1024*1024*8) == 0) {
xil_printf("  Writing: %d MB\r", (i * sizeof(u16)) / (1024*1024));
}
ddr_ptr[i] = (u16)(i & 0xFFFF);
}
xil_printf("\r\n  Verifying address test values...\r\n");
// Read phase - verify memory address values
for (u32 i = 0; i < total_locations; i += 1024) {
// Show progress every 16MB
if (i % (1024*1024*8) == 0) {
xil_printf("  Reading: %d MB\r", (i * sizeof(u16)) / (1024*1024));
}
read_value = ddr_ptr[i];
expected_value = (u16)(i & 0xFFFF);
if (read_value != expected_value) {
// Report first few errors in detail
if (address_errors < 10) {
xil_printf("\r\n  Address Error at 0x%08x: Expected 0x%04x, Read 0x%04x",
(u32)&ddr_ptr[i], expected_value, read_value);
}
address_errors++;
}
}
// Data pattern tests
xil_printf("\r\n\r\nRunning walking ones test...\r\n");
// Test patterns: walking 1's
for (u32 pattern_bit = 0; pattern_bit < DDR_WIDTH; pattern_bit++) {
test_pattern = (1 << pattern_bit);
// Write pattern to all locations
xil_printf("  Writing pattern 0x%04x\r", test_pattern);
for (u32 i = 0; i < total_locations; i += 1024) {
ddr_ptr[i] = (u16)test_pattern;
}
// Read and verify
xil_printf("\r  Verifying pattern 0x%04x\r", test_pattern);
for (u32 i = 0; i < total_locations; i += 1024) {
read_value = ddr_ptr[i];
if (read_value != test_pattern) {
// Report first few errors in detail
if (data_errors < 10) {
xil_printf("\r\n  Data Error at 0x%08x: Expected 0x%04x, Read 0x%04x",
(u32)&ddr_ptr[i], test_pattern, read_value);
}
data_errors++;
}
}
}
// Alternating pattern test (0xA5A5, 0x5A5A)
xil_printf("\r\n\r\nRunning alternating pattern test...\r\n");
// Test with 0xA5A5 pattern
test_pattern = 0xA5A5;
// Write pattern
xil_printf("  Writing pattern 0x%04x\r", test_pattern);
for (u32 i = 0; i < total_locations; i += 1024) {
ddr_ptr[i] = (u16)test_pattern;
}
// Read and verify
xil_printf("\r  Verifying pattern 0x%04x\r", test_pattern);
for (u32 i = 0; i < total_locations; i += 1024) {
read_value = ddr_ptr[i];
if (read_value != test_pattern) {
// Report first few errors in detail
if (data_errors < 20) {
xil_printf("\r\n  Data Error at 0x%08x: Expected 0x%04x, Read 0x%04x",
(u32)&ddr_ptr[i], test_pattern, read_value);
}
data_errors++;
}
}
// Test with inverted 0x5A5A pattern
test_pattern = 0x5A5A;
// Write pattern
xil_printf("\r  Writing pattern 0x%04x\r", test_pattern);
for (u32 i = 0; i < total_locations; i += 1024) {
ddr_ptr[i] = (u16)test_pattern;
}
// Read and verify
xil_printf("\r  Verifying pattern 0x%04x\r", test_pattern);
for (u32 i = 0; i < total_locations; i += 1024) {
read_value = ddr_ptr[i];
if (read_value != test_pattern) {
// Report first few errors in detail
if (data_errors < 30) {
xil_printf("\r\n  Data Error at 0x%08x: Expected 0x%04x, Read 0x%04x",
(u32)&ddr_ptr[i], test_pattern, read_value);
}
data_errors++;
}
}
// Calculate total errors
errors = address_errors + data_errors;
// Print test summary
xil_printf("\r\n\r\nDDR Memory Test Summary:\r\n");
xil_printf("  Locations tested: %d (at 1K intervals)\r\n", total_locations / 1024);
xil_printf("  Address test errors: %d\r\n", address_errors);
xil_printf("  Data pattern errors: %d\r\n", data_errors);
xil_printf("  Total errors: %d\r\n", errors);
if (errors == 0) {
xil_printf("  MEMORY TEST PASSED\r\n");
return 0;
} else {
xil_printf("  MEMORY TEST FAILED\r\n");
return 1;
}
}
// Function to display comprehensive test summary
void DisplayTestSummary(int failed_buttons, int failed_switches, int failed_pins, int memory_failed)
{
xil_printf("\r\n");
xil_printf("TEST SUMMARY\r\n");
xil_printf("============\r\n");
if (failed_buttons == 0) {
xil_printf("All push buttons PASSED functionality test!\r\n");
} else {
xil_printf("The following push buttons FAILED functionality test:\r\n");
for (int btn = 0; btn < NUM_BUTTONS; btn++) {
if (failed_buttons & (1 << btn)) {
xil_printf("- Button %d\r\n", btn + 1);
}
}
}
if (failed_switches == 0) {
xil_printf("\r\nAll slider switches PASSED functionality test!\r\n");
} else {
xil_printf("\r\nThe following slider switches FAILED functionality test:\r\n");
for (int sw = 0; sw < NUM_SWITCHES; sw++) {
if (failed_switches & (1 << sw)) {
xil_printf("- Switch %d\r\n", sw + 1);
}
}
}
if (failed_pins == 0) {
xil_printf("\r\nAll I/O pins PASSED connectivity test!\r\n");
} else {
xil_printf("\r\nThe following I/O pins FAILED connectivity test:\r\n");
for (int pin = 0; pin < NUM_PINS; pin++) {
if (failed_pins & (1 << pin)) {
xil_printf("- Pin %d\r\n", pin + 1);
}
}
}
if (memory_failed) {
xil_printf("\r\nDDR Memory test FAILED!\r\n");
} else {
xil_printf("\r\nDDR Memory test PASSED!\r\n");
}
// Overall test status
if (failed_buttons == 0 && failed_switches == 0 && failed_pins == 0 && !memory_failed) {
xil_printf("\r\n>>> ALL TESTS PASSED <<<\r\n");
} else {
xil_printf("\r\n!!! SOME TESTS FAILED !!!\r\n");
}
}
// Custom function for printing float values
int xil_printf_float(float x)
{
int integer, fraction, abs_frac;
integer = x;
fraction = (x - integer) * 100;
abs_frac = abs(fraction);
xil_printf("%d.%02d", integer, abs_frac);
return 0;
}
// Function to read and display System Monitor values
// Returns 0 if all voltages are within acceptable ranges, 1 otherwise
int ReadSystemMonitorValues(void)
{
u16 TempRawData, VccIntRawData, VccAuxRawData, VccBRamRawData;
float temp, vccint, vccaux, vccbram;
int voltage_error = 0;
// Wait for End Of Sequence bit to be set
while ((XSysMon_GetStatus(&SysMonInst) & XSM_SR_EOS_MASK) != XSM_SR_EOS_MASK);
// Read raw temperature data
TempRawData = XSysMon_GetAdcData(&SysMonInst, XSM_CH_TEMP);
// Read raw voltage data
VccIntRawData = XSysMon_GetAdcData(&SysMonInst, XSM_CH_VCCINT);
VccAuxRawData = XSysMon_GetAdcData(&SysMonInst, XSM_CH_VCCAUX);
VccBRamRawData = XSysMon_GetAdcData(&SysMonInst, XSM_CH_VBRAM);
// Convert raw data to actual values using Xilinx provided functions
temp = XSysMon_RawToTemperature(TempRawData);
vccint = XSysMon_RawToVoltage(VccIntRawData);
vccaux = XSysMon_RawToVoltage(VccAuxRawData);
vccbram = XSysMon_RawToVoltage(VccBRamRawData);
// Check voltages against acceptable ranges
voltage_error = CheckVoltages(vccint, vccaux, vccbram);
// Display values
xil_printf("---------------------------\r\n");
xil_printf("System Monitor Readings:\r\n");
xil_printf("  Temperature: ");
xil_printf_float(temp);
xil_printf(" °C");
// Add temperature warning if needed
if (temp > TEMP_CRITICAL) {
xil_printf(" !!! CRITICAL !!!");
} else if (temp > TEMP_WARNING) {
xil_printf(" ! WARNING !");
}
xil_printf("\r\n");
// Display voltages with status indicators
xil_printf("  VCCINT: ");
xil_printf_float(vccint);
xil_printf(" V");
if (vccint < VCCINT_MIN || vccint > VCCINT_MAX) {
xil_printf(" (OUT OF RANGE: ");
xil_printf_float(VCCINT_MIN);
xil_printf("-");
xil_printf_float(VCCINT_MAX);
xil_printf(" V)");
}
xil_printf("\r\n");
xil_printf("  VCCAUX: ");
xil_printf_float(vccaux);
xil_printf(" V");
if (vccaux < VCCAUX_MIN || vccaux > VCCAUX_MAX) {
xil_printf(" (OUT OF RANGE: ");
xil_printf_float(VCCAUX_MIN);
xil_printf("  VCCAUX: ");
xil_printf_float(vccaux);
xil_printf(" V");
}
if (vccaux < VCCAUX_MIN || vccaux > VCCAUX_MAX) {
xil_printf(" (OUT OF RANGE: ");
xil_printf_float(VCCAUX_MIN);
xil_printf("-");
xil_printf_float(VCCAUX_MAX);
xil_printf(" V)");
}
xil_printf("\r\n");
xil_printf("  VCCBRAM: ");
xil_printf_float(vccbram);
xil_printf(" V");
if (vccbram < VCCBRAM_MIN || vccbram > VCCBRAM_MAX) {
xil_printf(" (OUT OF RANGE: ");
xil_printf_float(VCCBRAM_MIN);
xil_printf("-");
xil_printf_float(VCCBRAM_MAX);
xil_printf(" V)");
}
xil_printf("\r\n");
xil_printf("---------------------------\r\n");
return voltage_error;
}
// Function to check if voltages are within acceptable ranges for Spartan-7
// Returns 0 if all voltages are within range, 1 otherwise
int CheckVoltages(float vccint, float vccaux, float vccbram)
{
int error = 0;
// Check VCCINT (1.0V nominal for Spartan-7)
if (vccint < VCCINT_MIN || vccint > VCCINT_MAX) {
error = 1;
}
// Check VCCAUX (1.8V nominal for Spartan-7)
if (vccaux < VCCAUX_MIN || vccaux > VCCAUX_MAX) {
error = 1;
}
// Check VCCBRAM (1.0V nominal for Spartan-7)
if (vccbram < VCCBRAM_MIN || vccbram > VCCBRAM_MAX) {
error = 1;
}
return error;
}

Testing

With the software application compiled, the bitstream and ELF file can be downloaded onto the target Arty board.

When testing this application, we need to ensure it not only passes, but also fails when expected—this helps validate the reliability of the self-test.

The first test to run is the memory test, which checks all DDR memory locations and address lines.

The push button test prompts the user to press and hold each button until a change is detected.

If no change is detected, the test times out and moves on to the next button. The failed test is added to a list of failed interfaces to be reported.

The same approach is taken with the switches—the application checks for any change in status.

Again, if the switch is not moved or fails to change status, the test will time out, and the error will be added to the list of failed interfaces.

The GPIO test for the Pmod connectors requires an external loopback connection. This connection will need to be moved from one Pmod pair to the next as the test progresses.

The requirement to change from pin to pin is prompted to the user over the serial port, guiding them through each step of the test.

If the connection is not made and the test progresses, or if there is a short-circuit failure, it will be recorded as a failure.

As the test completes, a summary of the test results will be displayed.

Wrap Up

This project has demonstrated that a comprehensive self-test application can be created simply and easily for an FPGA application.

Such an application is critical in many scenarios, as it enables the hardware to be tested and helps identify issues that may occur on the board during operation.

AMD, and the AMD Arrow logo, MicroBlaze, Spartan, Vitis, Vivado and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.