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I’ve created several projects that have explored and examined creating image processing solutions based around HDMI. To date, these projects have either used IO pins directly configured to receive / transmit TMDS or external HDMI Tx and Rx devices to convert parallel video to TMDS. These solutions have been used to implement HDMI 1.4 solutions that are capable of supporting resolutions of up to 4K at 24 Hz and 1080p at 120Hz.
This is good for many applications, however, to work with higher resolutions and frame rates (e.g. 4K at 60Hz), we need to use HDMI 2.0.
HDMI 2.0 requires support for up to 18 Gbps and the Tria Technologies AUBoard has been designed to support up to 6 Gbps, which enables 4Kx2K at 60Hz.
To do this, the AUBoard leverages the GTH transceivers provided by the AMD Artix™ UltraScale+™ FPGA.
In this project, we are going to take a look at how we can create a simple reference design that implements the image pass through. This will enable us to receive HDMI images from a camera or laptop and display them on a HDMI display at up to 4Kx2K resolution.
To do this, our design is going to include the following key elements
- AMD MicroBlaze™ processor - This will configure the IP within the design, and provide a simple menu for controlling the design and programming clock generators on the board.
- HDMI TX 1.4 / 2.0 subsystem - This will convert the video to be transmitted into HDMI format.
- HDMI RX 1.4./ 2.0 subsystem - This converts the received HDMI video in to a video stream
- Video Phy controller - This module interfaces with the GTH within the AMD Artix UltraScale+ FPGA. The Video Phy controller is the module which interfaces with the GTHs. It transmits the HDMI video provided by the HDMI TX 1.4 / 2.0 subsystem or passes received video to the HDMI RX 1.4 / 2.0 subsystem for decoding.
- Video test pattern generator – If no live video is provided, this gives the ability to generate an output test pattern for display.
The design will be created by modifying an AMD reference design.
LicensingTo be able to generate the bit stream, we need to have an evaluation license from AMD for the HDMI Tx and Rx subsystems and the Video Phy controller.
Connect to the AMD license manager and then enter HDMI as the product.
Generate a node locked license and download this license.
Using the AMD Vivado™ design suite license manager, select “Load License” and point to the license file just created.
This should be loaded into the AMD Vivado design suite license manager and be visible under the view license status option.
It is important you do this before generating the rest of the design, as the IP cores need to find this license when they are generated.
Creating the Reference DesignTo get started with creating the design in the AMD Vivado™ design suite, we are going to open a project which targets the VCU118.
Once the project is open, open the IP Library and select the HDMI 1.4 / 2.0 Receiver Subsystem.
This will add the IP to the project. Select the IP.
Right click on the selected IP and select “Open IP Example Design.”
When the dialog opens, select the location for the project to be stored.
This will open an example design targeting the VCU118. We need to change the target board to the AUBoard.
This will cause a flag that will say that there are several IPs which need attention..
Run the IP status report and you will see all of the IPs are locked and need upgrading due to a device change.
Update the selected IPs and re run the IP status report and the IP should now show as up to date.
The next step is to make changes in the video PHY controller to update for the GTHE4 provided on the AMD Artix™ UltraScale+™ device. Make sure you set the clock primitives to PLL.
The design should look as shown below.
In this design, video is passed from the HDMI Rx to the HDMI Tx, through the test pattern generator. To ensure the highest resolutions and framerates can be supported, video pixels are provided at either 2 pixels per clock or 4 pixels per clock (depending on the configuration of the modules).
The architecture of the design can be seen below. Externally, the transmit path uses a Display Port to HDMI translator, while the receiver uses a TMDS re-timer.
Internally, the video Phy controller, interfaces with the GTHs for Tx and Rx, and provides 3 HDMI data lanes for Tx and Rx. These lanes interface with the HDMI subsystems.
HDMI solutions require several IIC interfaces for the DDC associated with the HDMI Tx and Rx, which go directly to or from the HDMI Tx/Rx subsystems. These solutions also require IIC interfaces for the SN65DP159RGZT and TMS181 used for formatting the input and output GTHs.
We also need a second channel AXI IIC connected to the clock generator. This clock generator provides the GTH reference clock.
The IIC networks for the AUBoard is shown below.
Within the AMD MicroBlaze™ processor module, add a second AXI IIC and make its signals external.
Once this is completed, we are in a position to rebuild the image provided we have updated the constraints for the AUBoard.
# HDMI RX
#HDMI_RCLKOUT_P/N - MGTREFCLK1P/N - M7/M6
set_property PACKAGE_PIN M7 [get_ports HDMI_RX_CLK_P_IN]
create_clock -period 3.367 -name rx_mgt_refclk [get_ports HDMI_RX_CLK_P_IN]
#HDMI_RX_HPD - BANK65 T24
set_property PACKAGE_PIN T24 [get_ports RX_HPD_OUT]
set_property IOSTANDARD LVCMOS12 [get_ports RX_HPD_OUT]
#HDMI_RX_SNK_SCL = BANK65 N26
set_property PACKAGE_PIN N26 [get_ports RX_DDC_OUT_scl_io]
set_property IOSTANDARD LVCMOS12 [get_ports RX_DDC_OUT_scl_io]
set_property DRIVE 8 [get_ports RX_DDC_OUT_scl_io]
#HDMI_CTL_SDA = BANK65 T19
set_property PACKAGE_PIN T19 [get_ports RX_DDC_OUT_sda_io]
set_property IOSTANDARD LVCMOS12 [get_ports RX_DDC_OUT_sda_io]
set_property DRIVE 8 [get_ports RX_DDC_OUT_sda_io]
#HDMI_REC_CLK_P/N - BANK65 P25/P6 (FWD TO CLK GEN)
set_property PACKAGE_PIN P25 [get_ports RX_REFCLK_P_OUT]
set_property IOSTANDARD DIFF_SSTL12 [get_ports RX_REFCLK_P_OUT]
#set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports RX_REFCLK_P_OUT]
#set_property SLEW SLOW [get_ports RX_REFCLK_P_OUT]
#set_property SLEW SLOW [get_ports RX_REFCLK_N_OUT]
#HDMI_RX_PWR_DET - BANK65 U24
set_property PACKAGE_PIN U24 [get_ports RX_DET_IN]
set_property IOSTANDARD LVCMOS12 [get_ports RX_DET_IN]
# HDMI TX
#CLK_297M_P/N - MGTREFCLK0P/N - P7/P6 (FROM CLK GENERATOR)
set_property PACKAGE_PIN P7 [get_ports TX_REFCLK_P_IN]
create_clock -period 3.367 -name tx_mgt_refclk [get_ports TX_REFCLK_P_IN]
#HDMI_TX_CLK_P/N - BANK65 - T25/U25
set_property PACKAGE_PIN T25 [get_ports HDMI_TX_CLK_P_OUT]
set_property IOSTANDARD DIFF_HSUL_12 [get_ports HDMI_TX_CLK_P_OUT]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports HDMI_TX_CLK_P_OUT]
set_property SLEW SLOW [get_ports HDMI_TX_CLK_P_OUT]
set_property SLEW SLOW [get_ports HDMI_TX_CLK_N_OUT]
#HDMI_TX_HPD - BANK65 - W21
set_property PACKAGE_PIN W21 [get_ports TX_HPD_IN]
set_property IOSTANDARD LVCMOS12 [get_ports TX_HPD_IN]
#HDMI_TX_SRC_SCL - BANK65 - R25
set_property PACKAGE_PIN R25 [get_ports TX_DDC_OUT_scl_io]
set_property IOSTANDARD LVCMOS12 [get_ports TX_DDC_OUT_scl_io]
set_property DRIVE 8 [get_ports TX_DDC_OUT_scl_io]
#HDMI_TX_SRC_SDA - BANK65 - R26
set_property PACKAGE_PIN R26 [get_ports TX_DDC_OUT_sda_io]
set_property IOSTANDARD LVCMOS12 [get_ports TX_DDC_OUT_sda_io]
set_property DRIVE 8 [get_ports TX_DDC_OUT_sda_io]
# UART
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
#UART_TX - BANK84 - AF15 (SWAPPED AT TRANSLATOR U23 - MAY NEED CROSSING)
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
set_property PACKAGE_PIN AF15 [get_ports RS232_UART_txd]
set_property IOSTANDARD LVCMOS18 [get_ports RS232_UART_txd]
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
#UART_RX - BANK84 - AF14 (SWAPPED AT TRANSLATOR U23 - MAY NEED CROSSING)
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
set_property PACKAGE_PIN AF14 [get_ports RS232_UART_rxd]
set_property IOSTANDARD LVCMOS18 [get_ports RS232_UART_rxd]
# Misc
#LED1 - BANK85 - A10
set_property PACKAGE_PIN A10 [get_ports LED0]
set_property IOSTANDARD LVCMOS33 [get_ports LED0]
#LED2 - BANK85 - B10 - CLKGEN RESET
set_property PACKAGE_PIN B10 [get_ports {LED1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED1[0]}]
#LED3 - BANK85 - B11 - CLKGEN LOL
set_property PACKAGE_PIN B11 [get_ports LED2]
set_property IOSTANDARD LVCMOS33 [get_ports LED2]
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
#RST_CLOCK_N - BANK66 - G22
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
set_property PACKAGE_PIN G22 [get_ports {IDT_8T49N241_RST_OUT[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports {IDT_8T49N241_RST_OUT[0]}]
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
#PLL_LOCKED - BANK66 - F22
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
set_property PACKAGE_PIN F22 [get_ports IDT_8T49N241_LOL_IN]
set_property IOSTANDARD LVCMOS12 [get_ports IDT_8T49N241_LOL_IN]
#HDMI_TX_EN - BANK65 - Y23
set_property PACKAGE_PIN Y23 [get_ports {TX_EN_OUT[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports {TX_EN_OUT[0]}]
#HDMI_TX_CEC - BANK65 - AA23
set_property PACKAGE_PIN AA23 [get_ports {TX_CLKSEL_OUT[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports {TX_CLKSEL_OUT[0]}]
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
#NO I2C ENABLE ON - NO CONNECTION POINT TO THE FPGA - TIE TO TESTPOINT
#BANK84 HEADER J27 PIN2 - IO_BANK84_AD14 - AD14
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
#set_property PACKAGE_PIN AD14 [get_ports {RX_I2C_EN_N_OUT[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {RX_I2C_EN_N_OUT[0]}]
#sys_diff_clock_clk_p/n - SYSCLK_P/N - Bank64 - AD21 / AE21
set_property PACKAGE_PIN AD21 [get_ports sys_diff_clock_clk_p]
set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_diff_clock_clk_p]
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
#reset - SRESET - BANK65 - P19 (GPIO_SW1 - ACTIVE HIGH)
#&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
set_property PACKAGE_PIN P19 [get_ports reset]
set_property IOSTANDARD LVCMOS12 [get_ports reset]
# I2C
#HDMI_CTL_SCL - BANK65 - R22
set_property PACKAGE_PIN R22 [get_ports HDMI_CLK_IIC_scl_io]
set_property IOSTANDARD LVCMOS12 [get_ports HDMI_CLK_IIC_scl_io]
set_property DRIVE 8 [get_ports HDMI_CLK_IIC_scl_io]
#HDMI_CTL_SDA - BANK65 -R23
set_property PACKAGE_PIN R23 [get_ports HDMI_CLK_IIC_sda_io]
set_property IOSTANDARD LVCMOS12 [get_ports HDMI_CLK_IIC_sda_io]
set_property DRIVE 8 [get_ports HDMI_CLK_IIC_sda_io]
#SCL_SCLK - BANK85 -B9
set_property PACKAGE_PIN B9 [get_ports GTH_CLK_IIC_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports GTH_CLK_IIC_scl_io]
set_property DRIVE 8 [get_ports GTH_CLK_IIC_scl_io]
#SDA_nCS - BANK85 - A9
set_property PACKAGE_PIN A9 [get_ports GTH_CLK_IIC_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports GTH_CLK_IIC_sda_io]
set_property DRIVE 8 [get_ports GTH_CLK_IIC_sda_io]
#####
## End
#####
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 31.9 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]Once the project is built, you should see the implementation details as shown below.
Export the XSA from the AMD Vivado™ design suite such that we can create the application software.Application Software Development
With the XSA available, we can create a simple hello world application in AMD Vitis™ unified software platform. This hello world application will create a platform and application. Compiling and running the hello world application will pipe clean the process, ensuring we can generate and run an application on the AMD MicroBlaze processor.
Now we know we have a viable system and can execute programs on the AMD MicroBlaze™ processor we need to create the application software for the HDMI pass through.
Within the platform, open the platform.spr file and select the Board Support Package. Under the board support package, scroll down to find the v_hdmi_rx_ss driver and select import examples.
This will provide us with a list of possible application examples. In this case, we are going to use the Passthrough_MicroBlaze.
This will create the application. However, we need to make a couple of changes in the main application example to ensure the clock generator chip is configured correctly.
The main modification is to the conditional compilation to change the I2C clock generator type being programmed. By default, the software expects to program a Si5324 device, while the AUBoard has a Renesas 8T49N24 clock generator device.
int I2cClk(u32 InFreq, u32 OutFreq)
{
int Status;
//#if (!defined XPS_BOARD_ZCU104)
#if (defined XPS_BOARD_ZCU104)
/* Free running mode */
if (InFreq == 0) {
Status = Si5324_SetClock((XPAR_IIC_0_BASEADDR),
(I2C_CLK_ADDR),
(SI5324_CLKSRC_XTAL),
(SI5324_XTAL_FREQ),
OutFreq);
if (Status != (SI5324_SUCCESS)) {
xil_printf("Error programming SI5324\r\n");
return 0;
}
}
/* Locked mode */
else {
Status = Si5324_SetClock((XPAR_IIC_0_BASEADDR),
(I2C_CLK_ADDR),
(SI5324_CLKSRC_CLK1),
InFreq,
OutFreq);
if (Status != (SI5324_SUCCESS)) {
xil_printf("Error programming SI5324\r\n");
return 0;
}
}
#else
/* Reset I2C controller before issuing new transaction.
* This is required torecover the IIC controller in case a previous
* transaction is pending.
*/
XIic_WriteReg(XPAR_IIC_0_BASEADDR, XIIC_RESETR_OFFSET,
XIIC_RESET_MASK);
/* Free running mode */
if (InFreq == 0) {
Status = IDT_8T49N24x_SetClock((XPAR_IIC_0_BASEADDR),
(I2C_CLK_ADDR),
(IDT_8T49N24X_XTAL_FREQ),
OutFreq,
TRUE);
if (Status != (XST_SUCCESS)) {
print("Error programming IDT_8T49N241\r\n");
return 0;
}
}
/* Locked mode */
else {
Status = IDT_8T49N24x_SetClock((XPAR_IIC_0_BASEADDR),
(I2C_CLK_ADDR),
InFreq,
OutFreq,
FALSE);
if (Status != (XST_SUCCESS)) {
print("Error programming IDT_8T49N241\r\n");
return 0;
}
}
#endif
return 1;
}To ensure the software application can fit within the 256KB of memory provided, set the optimization level to O1.
Once we have made these changes, we can build the application and debug it on the board. The complete source code is available in the git project here.
Board Set UPThe hardware set up is very straightforward. We need to provide an HDMI sink and an HDMI source.
The HDMI sink(s) for initial testing was a Samsung monitor which supports 4K and a small monitor which supports 1080p. The HDMI source was a 4K sports camera, which could also change output modes.
Ensure the User DIP switch 1 is set to “off.” This switch controls the FPGA reset. The FPGA reset is active high, setting the switch low ensures the system is not in reset. This allows the AMD MicroBlaze processor to execute its applications and the video pipeline to process video.
Turn on the board and download the application for debugging.
Run the application with the HDMI sink and source connected with the camera set for 1080P. It should show an image being passed through.
Running the application will result in a menu being output over the UART. Using this menu, we are able to control the application running on the AMD MicroBlaze processor. In addition, we can also extract information on the configuration and performance of the image processing pipeline.
Pressing “i” will provide information on the HDMI TX and RX subsystems.
We can also extract the GTH logs over the terminal.
We can see the updated resolution after connecting the HDMI sink to a 4K capable monitor.
The AUBoard provides the perfect platform for developers interested in creating solutions for high resolution imaging. Thanks to the GTHs provided by the AMD Artix UltraScale+ FPGA, the AUBoard supports HDMI 2.0 resolutions and framerates. What is nice about this solution is that the logic resources remaining after implementing this pass through is very low. As such, it leaves over 70% of the AU15P resources free for use to implement image processing algorithms.
We will come back to this platform soon and look at how we are able to implement image processing filters within the pipeline.
AMD, and the AMD Arrow logo, Artix, MicroBlaze, UltraScale+, Vitis, Vivado, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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