Published June 22, 2026 © MIT

Altera FPGA Project 1: 4-digit decade counter

Design and implementation of a 4-digit decade counter with an Altera FPGA development board and a 7-segment display.

BeginnerFull instructions provided85

Altera FPGA Project 1: 4-digit decade counter

Things used in this project

Hardware components

Altera Cyclone IV FPGA Development Board

The vendor sells the USB cable and blaster to respectively power the board and program the FPGA.

Software apps and online services

Intel Quartus Prime 20.1

Story

Introduction

This project was the first RTL design I implemented on an FPGA to interface it with an external component. I had previously experimented with the Altera MAX II EPM240 CPLD to implement simple digital logic such as multiplexers, decoders, counters for blinking LEDs, and even UART transmitters. Although I had a lot of fun programming this CPLD, it didn't take long for me to realize that I wasn't going to accomplish much with just 240 logic elements. I invested in an FPGA board and ended up choosing the Altera Cyclone IV EP4CE6E22C8N board on AliExpress for its relatively lower cost and assortment of onboard peripherals.

Being the first project with my new board, I decided to do something "Hello Worldy" that didn't involve blinking an LED, since I had already tried that with my CPLD. I eventually went with the 4-digit 7-segment display on the board and tasked myself to create a counter that counts from 0 to 9999, incrementing every second and wrapping around to 0 from the maximum value of 9999. My HDL of choice was VHDL as it was the language I was familiar with at the time.

Hardware

The 4-digit 7-segment display on the EP4CE6E22C8N board has a common anode configuration. Since the anodes are tied to a common terminal, a high voltage is required to activate each digit of the device so that the LEDs in the segments can be independently controlled (turned on using a low voltage). All four digits share the same pins for controlling individual segments (they are multiplexed). As a result of the multiplexed pins, data with distinct digits can only be displayed by selecting one digit of the 7-segment display at a time, effectively displaying the value for each digit and quickly switching to the next such that the human eye won't be able to perceive the transition.

FPGA board's common anode 4-digit 7-segment display

RTL design

The design consists of three VHDL files/modules, namely: seg_display.vhd, seg_counter.vhd, and seg_rom.vhd. The logic/bit combinations for displaying numbers 0 to 9 are stored in the ROM module. The counter module increments from 0 to 9 at a rate determined by the place value of the digit on the 7-segment display. There are 4 digits: ones, tens, hundreds, and thousands. Counters are instantiated to update the value of the digits such that the counter for the next digit (to the left) is 10 times slower than the previous. Although this design works, it is very inefficient because it requires four active counters. A better solution is to convert the values to be displayed from binary to BCD using the Double Dabble algorithm (I learnt this several months later). The segment display VHDL module instantiates the counters and ROM module and also switches between the digits of the 7-segment display in order to give a proper display of distinct digits as explained in the Hardware section of this post.

Building the project

I made a few adjustments to the project over the years by making it somewhat platform-independent. You can successfully build it on Windows and Ubuntu without issues using Tcl scripts. Kindly check the link to my GitHub repository for additional documentation with instructions on how to do this if you're interested.

Video demo

Attached to this Hackster post is a link to a video demonstrating the project in action: Demo

What can be improved

I created this project back in 2024 when I was still new to RTL design and HDLs. Some of the major improvements that can be made include:

Replacing the four counters with a simple logic that converts from binary to BCD, and using the BCD values to drive the display.
Writing one generic/customizable counter module that can be instantiated in different parts of the design with appropriate parameters.
The design uses an asynchronous reset. It'll be better to use an asynchronous reset that de-asserts synchronously in order to prevent metastability issues.
A top-level file with only wired-up instantiations of other design modules. This version uses the seg_display.vhd as the top design but also includes a lot of logic.

Thanks for reading.

Code

--MIT License
--
--Copyright (c) 2024 Olaoluwa Raji
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;

-- Project: 0000 to 9999 counter. 

-- Common anode 7 segment display.
-- Logic low:  Activates the LEDs.
-- Logic high: Deactivates the LEDs.
-- System clock (clk): 50MHz.
-- 10KHz (to drive the 4 counters for each digit).
-- 10,000 system clock cycles (counter, shift register, and ...
-- ROM index counter) to switch from one digit to another.

-- Asynchronous reset (active low).

entity seg_display is
   port(rst_n: in std_logic;
        clk:   in std_logic;
        seg:  out std_logic_vector(6 downto 0);
        sel:  out std_logic_vector(3 downto 0));
end seg_display;

architecture seg_display_rtl of seg_display is
   constant TIME_TO_SWITCH_DIGIT: integer := 9_999;
   type digit_type is array(0 to 3) of std_logic_vector(3 downto 0);
   ------------------------------------------------------------------
   signal digit:       digit_type;
   signal count:       unsigned(15 downto 0);
   signal shift_reg:   std_logic_vector(3 downto 0);
   signal digit_index: unsigned(2 downto 0);
begin   
   -- Enables time-based digit switching
   digit_switching_counter: process(rst_n,clk)
   begin
      if rst_n = '0' then
         count <= (others => '0');
      elsif rising_edge(clk) then
         if count = to_unsigned(TIME_TO_SWITCH_DIGIT,count'length) then 
            count <= (others => '0');
         else
            count <= count + 1;
         end if;
      end if;
   end process;
   
   -- Select a digit using the switching counter and shift register
   sel <= shift_reg;
   
   shift_register: process(rst_n,clk)
   begin
      if rst_n = '0' then
         shift_reg <= "1110"; -- select 'units' digit by default
      elsif rising_edge(clk) then
         if count = to_unsigned(TIME_TO_SWITCH_DIGIT,count'length) then
            shift_reg(3 downto 1) <= shift_reg(2 downto 0);
            shift_reg(0) <= shift_reg(3);
         end if;
      end if;
   end process;
   
   -- Counter to select which digit should be loaded into the ROM
   digit_index_counter: process(rst_n,clk)
   begin
      if rst_n = '0' then
         digit_index <= (others => '0');
      elsif rising_edge(clk) then
         if count = to_unsigned(TIME_TO_SWITCH_DIGIT,count'length) then
            if digit_index = to_unsigned(3,digit_index'length) then
               digit_index <= (others => '0');
            else
               digit_index <= digit_index + 1;
            end if;
         end if;
      end if;  
   end process;
   
   -- Counter for 'units' digit
   counter_1: entity work.seg_counter(seg_counter_rtl)
   generic map(PLACE_VALUE => 1)
   port map(rst_n          => rst_n, 
            clk            => clk, 
            digit_out      => digit(0));
   
   -- Counter for 'tens' digit          
   counter_2: entity work.seg_counter(seg_counter_rtl)
   generic map(PLACE_VALUE => 10)
   port map(rst_n          => rst_n, 
            clk            => clk, 
            digit_out      => digit(1));
   
   -- Counter for 'hundreds' digit         
   counter_3: entity work.seg_counter(seg_counter_rtl)
   generic map(PLACE_VALUE => 100)
   port map(rst_n          => rst_n, 
            clk            => clk, 
            digit_out      => digit(2));
   
   -- Counter for 'thousands' digit     
   counter_4: entity work.seg_counter(seg_counter_rtl)
   generic map(PLACE_VALUE => 1000)
   port map(rst_n          => rst_n, 
            clk            => clk, 
            digit_out      => digit(3)); 
   
   -- Converts a digit's current value to signals to drive the display
   rom: entity work.seg_rom(seg_rom_rtl)
   port map(addr     => digit(to_integer(digit_index)), 
            data_out => seg);
   
end seg_display_rtl;

--MIT License
--
--Copyright (c) 2024 Olaoluwa Raji
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- 4-bit generic counter for each digit or segment ...
-- of the 4-digit 7 segment display.

entity seg_counter is
   generic(PLACE_VALUE: integer := 1);
   
   port(rst_n:      in std_logic;
        clk:        in std_logic;
        digit_out: out std_logic_vector(3 downto 0));
end seg_counter;

architecture seg_counter_rtl of seg_counter is
   -- System clock: 50 MHz 
   -- 1 period of 10 kHz clock: 5000 cycles of system clock
   -- 10,000 periods of 10 kHz clock = 1 second
   -- Half cycle for 10 kHz: 2500
   -- Maximum clock cycles (10 kHz) for a digit = 10,000 x place value
   constant HALF_CYCLE: integer := 2499;
   constant DIGIT_CLKS: integer := (PLACE_VALUE * 10_000) - 1;
   ------------------------------------------------------------------
   signal cnt1:  integer range 0 to HALF_CYCLE;
   signal cnt2:  integer range 0 to DIGIT_CLKS;
   signal tick:  std_logic; 
   signal rise:  std_logic; -- Rising edge of 10 kHz clock
   signal digit: unsigned(3 downto 0);
begin
   clock_10kHz: process(rst_n,clk)
   begin
      if rst_n = '0' then
         cnt1 <=  0;
         tick <= '1';
      elsif rising_edge(clk) then
         if cnt1 = HALF_CYCLE then
            cnt1 <= 0;
            tick <= not tick;
         else
            cnt1 <= cnt1 + 1;
         end if;
      end if;
   end process;
   
   -- Rising edge detector
   rise <= '1' when tick = '1' and cnt1 = 0 else '0';
   
   clock_counter_10kHz: process(rst_n,clk)
   begin
      if rst_n = '0' then
         cnt2 <= 0;
      elsif rising_edge(clk) then
         if rise = '1' then
            if cnt2 = DIGIT_CLKS then
               cnt2 <= 0;
            else
               cnt2 <= cnt2 + 1;
            end if;
         end if;
      end if;
   end process;
   
   -- Buffered output
   digit_out <= std_logic_vector(digit);  
   
   digit_counter: process(rst_n,clk)
   begin
      if rst_n = '0' then
         digit <= (others => '0');     
      elsif rising_edge(clk) then
         if rise = '1' and cnt2 = DIGIT_CLKS then
            if digit = to_unsigned(9,digit'length) then
               digit <= (others => '0');
            else
               digit <= digit + 1;
            end if;        
         end if;
      end if;
   end process;
   
end seg_counter_rtl;

--MIT License
--
--Copyright (c) 2024 Olaoluwa Raji
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- ROM: to map digits to signals to drive the 7 segment display.
-- g,f,e,d,c,b,a are the individual LED segments.
entity seg_rom is
  port(addr:      in std_logic_vector(3 downto 0);
       data_out: out std_logic_vector(6 downto 0));
end seg_rom;

architecture seg_rom_rtl of seg_rom is
   type rom_type is array(0 to 9) of std_logic_vector(6 downto 0);
   --------------------------------"gfedcba"
   constant ROM: rom_type := (0 => "1000000",
                              1 => "1111001",
                              2 => "0100100",
                              3 => "0110000",
                              4 => "0011001",
                              5 => "0010010",
                              6 => "0000010",
                              7 => "1111000",
                              8 => "0000000",
                              9 => "0010000");
begin
   data_out <= ROM(to_integer(unsigned(addr)));
end seg_rom_rtl;

Credits

Olaoluwa Raji

2 projects • 2 followers

Embedded system design

Altera FPGA Project 1: 4-digit decade counter

Things used in this project

Hardware components

Software apps and online services

Story

Introduction

Hardware

RTL design

Building the project

Video demo

What can be improved

Schematics

RTL Schematic

FPGA Board Schematic

Code

seg_display.vhd

seg_counter.vhd

seg_rom.vhd

Github file

Credits

Olaoluwa Raji

Comments

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Altera FPGA Project 1: 4-digit decade counter

Altera FPGA Project 1: 4-digit decade counter

Things used in this project

Hardware components

Software apps and online services

Story

Introduction

Hardware

RTL design

Building the project

Video demo

What can be improved

Schematics

RTL Schematic

FPGA Board Schematic

Code

seg_display.vhd

seg_counter.vhd

seg_rom.vhd

Github file

Credits

Olaoluwa Raji

Comments

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