PsySc0rpi0n
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STM32F407VET6 DIYMore. cc board programming

Using different tools to program a very simply Blinky code

BeginnerFull instructions provided84
STM32F407VET6 DIYMore. cc board programming

Things used in this project

Hardware components

stm32f407vet6
×1
Segger j-link Base
×1

Software apps and online services

openOCD
To talk to the chip and upload the code
gdb-multiarch
arm-none-eabi-gcc
arm-none-eabi-objcopy
libopencm3

Story

Read more

Code

test.c

C/C++
This is the main file with the code
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/stm32/gpio.h>

void delay(void){
    for(int i = 0; i < 1000000; i++)
        __asm__("nop");
}

int main(void){
    rcc_clock_setup_pll(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]);
    rcc_periph_clock_enable(RCC_GPIOA);

    gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO1);

    while(1){
        gpio_toggle(GPIOA, GPIO1);
        delay();
    }
    return 0;
}

Linker Script

Assembly x86
It's just the most important part to make the code work. Defenition of memory regions and init vectors
/*
 * This file is part of the libopencm3 project.
 *
 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/* Generic linker script for STM32 targets using libopencm3. */

/* Memory regions must be defined in the ld script which includes this one. */

/* Enforce emmition of the vector table. */
EXTERN (vector_table)

MEMORY
{
    rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
    ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
}

/* Define sections. */
SECTIONS
{
	. = ORIGIN(rom);

	.text : {
		*(.vectors)	/* Vector table */
		*(.text*)	/* Program code */
		. = ALIGN(4);
		*(.rodata*)	/* Read-only data */
		. = ALIGN(4);
        __preinit_array_start = .;
        KEEP (*(.preinit_array))
        __preinit_array_end = .;
        __init_array_start = .;
        KEEP (*(SORT(.init_array.*)))
        KEEP (*(.init_array))
        __init_array_end = .;
        __fini_array_start = .;
        KEEP(*(.fini_array))
        KEEP(*(SORT(.fini_array.*)))
        __fini_array_end = .;

		_etext = .;
	} >rom

	. = ORIGIN(ram);

    _data_loadaddr = LOADADDR(.data);

	.data : {
		_data = .;
		*(.data*)	/* Read-write initialized data */
		. = ALIGN(4);
		_edata = .;
	} >ram AT >rom

	.bss : {
        _bss = .;
		*(.bss*)	/* Read-write zero initialized data */
		*(COMMON)
		. = ALIGN(4);
		_ebss = .;
	} >ram /* AT >rom */

	/*
	 * The .eh_frame section appears to be used for C++ exception handling.
	 * You may need to fix this if you're using C++.
	 */
    _stack = ORIGIN(ram) + LENGTH(ram);
	/DISCARD/ : { *(.eh_frame) }

	. = ALIGN(4);
	end = .;
}

Makefile

Makefile
Where the magic happens
#-------- Project Configuration --------
BINARY		= test
OPENCM3_DIR = ../libopencm3
LDSCRIPT	= ld/libopencm3_stm32f4.ld
LIBNAME		= opencm3_stm32f4

#-------- Toolchain --------
CC			= arm-none-eabi-gcc
OBJCOPY		= arm-none-eabi-objcopy
GDB			= gdb-multiarch

#-------- OpenOCD Settings --------
OOCD			= openocd
OOCD_INTERFACE	= interface/jlink.cfg
OOCD_TARGET		= target/stm32f4x.cfg
OOCD_FLAGS		= -f $(OOCD_INTERFACE) -c "transport select swd" -f $(OOCD_TARGET)

#-------- Compiler and Linker Flags --------
ARCH_FLAGS	= -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16

CFLAGS 		= $(ARCH_FLAGS)
CFLAGS 		+= -Iinclude -I$(OPENCM3_DIR)/include -DSTM32F4
CFLAGS		+= -Wall -O2 -Wextra -pedantic -Werror -g

LDFLAGS		= -L$(OPENCM3_DIR)/lib -T$(LDSCRIPT) -nostartfiles $(ARCH_FLAGS)
LDFLAGS		+= -Wl,--undefined=vector_table
LDLIBS		= -l$(LIBNAME)

#-------- Files & Paths --------
SOURCES		= $(wildcard src/*.c)
# This maps src/filename.c to object/filename.o
OBJECTS		= $(patsubst src/%.c, object/%.o, $(SOURCES))

#-------- Rules --------
all: directories bin/$(BINARY).bin

# 1. Create directories if they don't exist
directories:
	@mkdir -p bin object

# 2. Compile .c files to .o files
object/%.o: src/%.c
	@echo "Compiling $<..."
	@$(CC) $(CFLAGS) -c $< -o $@

# 3. Link .o files to .elf files
bin/$(BINARY).elf: $(OBJECTS)
	@echo "Linking $@..."
	@$(CC) $(OBJECTS) $(LDFLAGS) $(LDLIBS) -o $@

# 4. Convert .elf files to .bin files
bin/$(BINARY).bin: bin/$(BINARY).elf
	@echo "Creating binary $@..."
	@$(OBJCOPY) -O binary $< $@
	@echo "Done!..."

# 5. Flash via J-link
upload: all
	@echo "Flashing via OpenOCD..."
	@$(OOCD) $(OOCD_FLAGS) -c "program bin/$(BINARY).elf verify reset exit"

# 6. Debug via GDB
# This assumes OpenOCD is already running in another terminal window
debug: all
	$(GDB) -ex "target extended-remote :3333" \
		-ex "monitor reset halt" \
		-ex "load" \
		-ex "monitor reset halt" \
		-ex "tbreak main" \
		-ex "continue" \
		bin/$(BINARY).elf

clean:
	rm -rf object bin

.PHONY: all directories clean upload debug

Basic Circuitry

Plain text
Circuitry for BOOT0, BOOT1, Push Button 1 and 2.
$ 1 0.000005 10.20027730826997 50 5 50 5e-11
r 288 96 368 96 0 10000
r 288 64 368 64 0 10000
r 160 96 240 96 0 330
r 160 64 240 64 0 330
r 432 96 432 176 0 1000
c 512 96 512 176 4 0.000001 0.001 0.001 0.1
w 512 64 512 96 0
w 432 96 432 64 0
g 432 176 432 192 0 0
g 512 176 512 192 0 0
w 368 96 432 96 0
207 256 96 256 144 4 BOOT1/PB2\s(STM32F407VET6)
207 256 64 256 16 4 BOOT0\s(STM32F407VET6)
w 240 64 256 64 0
w 256 64 288 64 0
w 256 96 240 96 0
w 256 96 288 96 0
207 160 64 112 64 4 BOOT0\spin\sheader
207 160 96 112 96 4 BOOT1\spin\sheader
c 576 96 576 176 4 0.00001 0.001 0.001 0.1
w 576 96 576 64 0
w 576 64 512 64 0
g 576 176 576 192 0 0
w 368 64 432 64 0
w 512 64 432 64 0
R 432 64 432 16 0 0 40 3.3 0 0 0.5
s 64 272 128 272 0 0 false
s 320 304 384 304 0 1 false
g 16 272 16 304 0 0
g 272 304 272 336 0 0
w 16 272 64 272 0
w 272 304 320 304 0
c 128 304 128 368 4 0.00001 0.001 0.001 0
w 128 272 128 304 0
g 128 368 128 384 0 0
r 128 272 192 272 0 10000
R 224 272 224 224 0 0 40 3.3 0 0 0.5
r 224 304 224 368 0 1000
w 224 272 224 304 0
g 224 368 224 384 0 0
207 128 272 128 224 4 NRST\s(STM32F407VET6)
w 192 272 224 272 0
r 384 304 464 304 0 10000
c 464 304 464 384 4 0.00001 0.001 0.001 0.1
c 560 304 560 384 4 0.00001 0.001 0.001 0.1
g 464 384 464 400 0 0
g 560 384 560 400 0 0
w 464 304 560 304 0
207 464 304 464 256 4 VDD\s(STM32F407VET6)
R 560 304 560 256 0 0 40 3.3 0 0 0.5
b 256 215 615 418 0
x 275 400 435 403 4 16 Push\sButton\s1\scircuitry
b 19 209 250 420 0
x 19 416 179 419 4 16 Push\sButton\s2\scircuitry
b 16 16 625 208 0
x 42 182 240 185 4 16 BOOT0\s\a\a\sBOOT1\scircuitry

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PsySc0rpi0n
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