QMTECH Zynq Board
Read moreThe QMTECH has a Zynq XC7Z020-1CLG484C with 512MB Micron DDR3, MT41K256M16TW-107:P chip. Ethernet and external USB A connector.
There is not a JTAG to USB converter on the board, but there is firmware to turn a PICO 2 into a Xilinx Virtual Cable (XVC). Allowing to debug FPGA and embedded code with Vivado and Vitis.
BuildrootBuildroot is a tool that simplifies and automates the process of building a complete, bootable Linux system for embedded systems, using cross-compilation, and generating a root filesystem, kernel image, and bootloader
Getting startedThe tutorial is using Ubuntu 22.04.05 LTS on a Desktop I7-7700T CPU with a 1 TB SSD.
From the home directory:
mkdir -p projects/qmtech
cd projects/qmtech
git clone --recurse-submodules https://github.com/tcmichals/QMTECH.git
git clone https://gitlab.com/buildroot.org/buildroot.git
mkdir bld
cd bld
make -C ../buildroot/ O=$PWD BR2_EXTERNAL=$PWD/../QMTECH/zynq_qmtech_xc720 zynq_qmtech_xc720_defconfig
makeThe QMTECH github project has details to instruct buildroot to build the cross compiler tools for the Zynq 7020 processor, u-boot device tree information, and Linux device tree information. The BR2_EXTERNAL parameter instructs builroot where the external tree exists. Thus, user can have a tree outside of buildroot. For more details are here.
The command, make Will take about 30 minutes, depending on internet speed, SSD speed, etc. Buildroot is pulling a large number of tools, Linux and uboot source.
Once make is finished a sdcard image is created. You need a sdcard to image.
At the end of the build an sdcard image file is created. I use a USB SDCard reader.
Once you insert the USB SDCard reader in then:
dd if=images/sdcard.img of=/dev/<your sd card> bs=10MB
Insert the SD card and reboot. On the serial port you will a bash shell login.
Next article will go into detail on how to use Vivado to create the files for the SPL u-boot boot loader to configure the DDR and Zynq.
U-Boot SPL 2025.01 (Mar 18 2025 - 21:20:08 -0500)
Silicon version: 3
Trying to boot from MMC1
spl_load_image_fat: error reading image uImage, err - -22
U-Boot 2025.01 (Mar 18 2025 - 21:20:08 -0500)
CPU: Zynq 7z020
Silicon: v3.1
Model: QMTech ZedBoard board
DRAM: ECC disabled 512 MiB
Core: 20 devices, 14 uclasses, devicetree: board
Flash: 0 Bytes
NAND: 0 MiB
MMC: mmc@e0100000: 0
Loading Environment from FAT... *** Error - No Valid Environment Area found
*** Warning - bad env area, using default environment
In: serial@e0000000
Out: serial@e0000000
Err: serial@e0000000
Net:
ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id
Warning: ethernet@e000b000 (eth0) using random MAC address - 8a:33:56:38:f9:7d
eth0: ethernet@e000b000
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
1: linux
Retrieving file: /uImage
append: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait
Retrieving file: /system.dtb
## Booting kernel from Legacy Image at 02000000 ...
Image Name: Linux-6.6.0-xilinx
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 4884808 Bytes = 4.7 MiB
Load Address: 00008000
Entry Point: 00008000
Verifying Checksum ... OK
## Flattened Device Tree blob at 01f00000
Booting using the fdt blob at 0x1f00000
Working FDT set to 1f00000
Loading Kernel Image to 8000
Loading Device Tree to 1dabe000, end 1dac3bdc ... OK
Working FDT set to 1dabe000
Starting kernel ...
Booting Linux on physical CPU 0x0
Linux version 6.6.0-xilinx (tcmichals@hp) (arm-buildroot-linux-gnueabihf-gcc.br_real (Buildroot 2025.02-96-gd63e207eb8) 14.2.0, GNU ld (GNU Binutils)5
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: QMTECH z20 board
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x1f000000 on node -1
Zone ranges:
Normal [mem 0x0000000000000000-0x000000001fffffff]
HighMem empty
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000000000000-0x000000001fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
percpu: Embedded 12 pages/cpu s17940 r8192 d23020 u49152
Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
Built 1 zonelists, mobility grouping on. Total pages: 130048
mem auto-init: stack:all(zero), heap alloc:off, heap free:off
Memory: 491040K/524288K available (7168K kernel code, 251K rwdata, 2132K rodata, 1024K init, 147K bss, 16864K reserved, 16384K cma-reserved, 0K highm)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
rcu: Preemptible hierarchical RCU implementation.
rcu: RCU event tracing is enabled.
rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
GIC physical location is 0xf8f01000
L2C: platform modifies aux control register: 0x02060000 -> 0x02460000
L2C: DT/platform modifies aux control register: 0x02060000 -> 0x02460000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x46460001
rcu: srcu_init: Setting srcu_struct sizes based on contention.
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 167MHz, resolution 6ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x26703d7dd8, max_idle_ns: 440795208065 ns
Switching to timer-based delay loop, resolution 6ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 333.33 BogoMIPS (lpj=1666666)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
rcu: Max phase no-delay instances is 1000.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU1: Spectre v2: using BPIALL workaround
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (666.66 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered PF_NETLINK/PF_ROUTE protocol family
DMA: preallocated 256 KiB pool for atomic coherent allocations
thermal_sys: Registered thermal governor 'step_wise'
cpuidle: using governor menu
platform axi: Fixed dependency cycle(s) with /axi/interrupt-controller@f8f01000
amba f8801000.etb: Fixed dependency cycle(s) with /replicator/out-ports/port@1/endpoint
amba f8803000.tpiu: Fixed dependency cycle(s) with /replicator/out-ports/port@0/endpoint
amba f8804000.funnel: Fixed dependency cycle(s) with /replicator/in-ports/port/endpoint
amba f889c000.ptm: Fixed dependency cycle(s) with /axi/funnel@f8804000/in-ports/port@0/endpoint
amba f889d000.ptm: Fixed dependency cycle(s) with /axi/funnel@f8804000/in-ports/port@1/endpoint
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 26, base_baud = 6249999) is a xuartps
printk: console [ttyPS0] enabled
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
usb_phy_generic e0002000.phy0: dummy supplies not allowed for exclusive requests
mc: Linux media interface: v0.10
videodev: Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
vgaarb: loaded
clocksource: Switched to clocksource arm_global_timer
NET: Registered PF_INET protocol family
IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
NET: Registered PF_UNIX/PF_LOCAL protocol family
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp-with-tls transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 64
armv7-pmu f8891000.pmu: hw perfevents: no interrupt-affinity property, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=17 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
io scheduler mq-deadline registered
io scheduler kyber registered
io scheduler bfq registered
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
dma-pl330 f8003000.dma-controller: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
brd: module loaded
loop: module loaded
CAN device driver interface
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 39 (8a:33:56:38:f9:7d)
e1000e: Intel(R) PRO/1000 Network Driver
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
usbcore: registered new interface driver usb-storage
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
i2c_dev: i2c /dev entries driver
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
ledtrig-cpu: registered to indicate activity on CPUs
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=43
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
NET: Registered PF_INET6 protocol family
Segment Routing with IPv6
In-situ OAM (IOAM) with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered PF_PACKET protocol family
can: controller area network core
NET: Registered PF_CAN protocol family
can: raw protocol
can: broadcast manager protocol
can: netlink gateway - max_hops=1
Registering SWP/SWPB emulation handler
of-fpga-region fpga-region: FPGA Region probed
of_cfs_init
of_cfs_init: OK
mmc0: new high speed SDHC card at address aaaa
clk: Disabling unused clocks
ALSA device list:
mmcblk0: mmc0:aaaa SK32G 29.7 GiB
No soundcards found.
mmcblk0: p1 p2
EXT4-fs (mmcblk0p2): mounted filesystem 5f890d84-6c33-46ee-88f8-79f4b5ee7ead r/w with ordered data mode. Quota mode: disabled.
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel image (initmem) memory: 1024K
Run /sbin/init as init process
EXT4-fs (mmcblk0p2): re-mounted 5f890d84-6c33-46ee-88f8-79f4b5ee7ead r/w. Quota mode: disabled.
Seeding 256 bits without crediting
Saving 256 bits of non-creditable seed for next boot
Starting syslogd: OK
Starting klogd: OK
Running sysctl: OK
Starting network: OK
Starting crond: OK
Welcome to Buildroot
buildroot login:
CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.8 | VT102 | Offline | ttyUSB0
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