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This tutorial is on recreating Kria KV260 BIST firmware and app in 2025.1 Vitis/VIVADO.
A. OverviewThe KV260 BIST consists of VIVADO IP design or flow for taking camera input from MIPI -Rpi, IAS interfaces or encoding/decoding stream with VCU and IP packet with PS ethernet interfaces, so it is important reference while designing for custom MIPI or VCU based applications.
Anyone looking for vision and camera application on top of Kria can take this example. Also there are other kria vision apps which can also be referred.
Kria BIST is detail design for bringing up the major interfaces in the board.
At this tutorial we are recreating the KV260 BIST with 2025.1 tool version.
B. Steps performed:1. Git clone the repo – recursive approach or add vitis libraries later.
Option A [Recommended]:
git clone --recursive https://github.com/Xilinx/kria-vitis-platforms.gitOption B: Download source code ZIP from here: https://github.com/Xilinx/kria-vitis-platforms/releases/tag/v1.0.1
Extract it and then Clone :
git clone --recursive https://github.com/Xilinx/kria-vitis-platforms.gitNow copy the Vitis Libraries from here to v1.0.1
2. Goto KV260 directory
cd ./kv260/platforms/kv260_bist3. Now run the make command:
kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist$ make xsaThe BIST source is created in a way that it can be easily generated into block design and then XSA. It has less version dependent tcl based project sources. And it also has provided the full and all mandatory constraint PIN locations so user can refer those constrainting for custom carrier board based design to, where board awareness is not fully available,
4. You can see the terminal log, according to CPU/RAM availability on PC the design can get generated by around 30min.
5. Now you can lunch VIVADO and check the block design, resource usage and other info:
Expanded VIVADO block design looks like this:
We have expanded the MIPI capture pipeline (three pipeline are on MIPI) and VCU encoding/decoding pipeline
Picture Raspberry pi MIPI camera capture pipeline
MIPI IAS capture pipeline consists of MIPI IP, demosiacing, VPSS and video framebuffer to write that YUV format of data to memory.
6. KV260 BIST has been generated, now using XSA one can create the DTSI and then DTBO. The BIT inside XSA can be renamed as BIN and JSON file can be copy from Kria-App-firmware repo.
7. Now one can copy and load the firmware into KV260 (Petalinux or Ubuntu) and run the same KV260 python applications.
8. By following this BIST application one can also create own block design and integrated in Kria app flow.
9. XSA, BIT file can also be found at this github repo.
10. Build log is attached below section.
11. At next, we will copy these BIST firmware files to KV260 and run there with BIST docker App or with custom python/C++ app: https://github.com/xilinx/kria-bist
12. Similarly, one can generate other platforms of Kria app and refer those for custom design: https://github.com/Xilinx/kria-vitis-platforms/tree/main/kv260/platforms. When platform is prepared, the overlay is also less dependent to tool version, one can add DPU, ISP and other custom overlay on those platforms: https://github.com/Xilinx/kria-vitis-platforms/tree/main/kv260/overlays
The Git repo of this recreating BIST for KV260 in 2025.1 is at here: https://github.com/LogicTronixInc/Recreating-Kria-BIST-2025.1
Thank you for going through this tutorial!
For any queries on recreating BIST for KV260 on 2025.1 or later tools, please write us at info@logictronix.com
LogicTronix is AMD-Xilinx Partner for FPGA Design and ML Acceleration!
logictronix05@logictronix05-MS-7E26:/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms$ cd ./kv260_bist
ls
WARNING: [Common 17-259] Unknown Tcl command 'ls' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
dtsi
Makefile
scripts
xdc
logictronix05@logictronix05-MS-7E26:/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist$ make xsa
WARNING: [Common 17-259] Unknown Tcl command 'make xsa' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
/tools/Xilinx/2025.1/Vivado/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8
****** Vivado v2025.1 (64-bit)
**** SW Build 6140274 on Wed May 21 22:58:25 MDT 2025
**** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025
**** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025
**** Start of session at: Sun Jul 13 13:44:25 2025
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
source scripts/main.tcl -notrace
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:scu35:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/scu35/1.0/board.xml as part xcsu35p-sbvb625-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:v80:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/v80/1.0/board.xml as part xcv80-lsva4737-2mhp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.2/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.3/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.2/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:scu35:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/scu35/1.0/board.xml as part xcsu35p-sbvb625-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:v80:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/v80/1.0/board.xml as part xcv80-lsva4737-2mhp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.2/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.3/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.2/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/ip'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.1/Vivado/data/ip'.
Wrote : </media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.srcs/sources_1/bd/kv260_bist/kv260_bist.bd>
INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
INFO: [Device 21-403] Loading part xck26-sfvc784-2LV-c
WARNING: [BD 41-176] The physical port 'dl0_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl0_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl3_rxulpmesc' specified in the portmap, is not found on the block!
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-394] Exec TCL: all interface pins/ports are already connected to interface net '/mipi_phy_if_1'
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
WARNING: [BD 41-176] The physical port 'dl0_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl0_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl3_rxulpmesc' specified in the portmap, is not found on the block!
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-394] Exec TCL: all interface pins/ports are already connected to interface net '/mipi_phy_if_1'
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
deint_m_axi_mm_width = 128
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axi_mm/gpio_io_o> is being overridden by the user with net <net_reset_sel_axi_mm_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axi_mm/gpio_io_i> is being overridden by the user with net <net_reset_sel_axi_mm_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_o> is being overridden by the user with net <net_reset_sel_axis_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_i> is being overridden by the user with net <net_reset_sel_axis_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </deint_ss/m_axis_tuser> is being overridden by the user with net <net_deint_ss_m_axis_tuser>. This pin will not be connected as a part of interface connection <M_AXIS>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </deint_cc/s_axis_tuser> is being overridden by the user with net <net_deint_concat_dout>. This pin will not be connected as a part of interface connection <S_AXIS>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </deint_cc/m_axis_tuser> is being overridden by the user with net <net_deint_cc_m_axis_tuser>. This pin will not be connected as a part of interface connection <M_AXIS>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </dint/s_axis_video_TUSER> is being overridden by the user with net <net_deint_tuser_tap_Dout>. This pin will not be connected as a part of interface connection <s_axis_video>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
1
true
true
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
Slave segment '/axi_vdma/S_AXI_LITE/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0000_0000 [ 64K ]>.
Slave segment '/csc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0001_0000 [ 64K ]>.
Slave segment '/dint/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0002_0000 [ 64K ]>.
Slave segment '/hcr/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0003_0000 [ 64K ]>.
Slave segment '/hsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0004_0000 [ 64K ]>.
Slave segment '/ltr/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0005_0000 [ 64K ]>.
Slave segment '/reset_sel_axi_mm/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0006_0000 [ 64K ]>.
Slave segment '/reset_sel_axis/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0007_0000 [ 64K ]>.
Slave segment '/vcr_i/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0008_0000 [ 64K ]>.
Slave segment '/vcr_o/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0009_0000 [ 64K ]>.
Slave segment '/video_router/xbar/S_AXI_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x000A_0000 [ 64K ]>.
Slave segment '/vsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x000B_0000 [ 64K ]>.
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_i> is being overridden by the user with net <net_reset_sel_axis_gpio_io_i>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_o> is being overridden by the user with net <net_reset_sel_axis_gpio_io_i>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
0
true
true
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
Slave segment '/hsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0000_0000 [ 64K ]>.
Slave segment '/reset_sel_axis/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0001_0000 [ 64K ]>.
Slave segment '/vsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0002_0000 [ 64K ]>.
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
WARNING: [BD 41-176] The physical port 'dl0_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl0_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl3_rxulpmesc' specified in the portmap, is not found on the block!
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-394] Exec TCL: all interface pins/ports are already connected to interface net '/mipi_phy_if_1'
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
WARNING: [BD 41-176] The physical port 'dl0_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl0_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl3_rxulpmesc' specified in the portmap, is not found on the block!
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-394] Exec TCL: all interface pins/ports are already connected to interface net '/mipi_phy_if_1'
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
WARNING: [BD 41-176] The physical port 'dl0_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl0_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl3_rxulpmesc' specified in the portmap, is not found on the block!
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-394] Exec TCL: all interface pins/ports are already connected to interface net '/mipi_phy_if_1'
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
WARNING: [BD 41-176] The physical port 'dl0_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl0_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl1_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxinvalidcodehs' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl2_rxulpmesc' specified in the portmap, is not found on the block!
WARNING: [BD 41-176] The physical port 'dl3_rxulpmesc' specified in the portmap, is not found on the block!
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-394] Exec TCL: all interface pins/ports are already connected to interface net '/mipi_phy_if_1'
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
m_axi_mm_width = 128
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
deint_m_axi_mm_width = 128
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axi_mm/gpio_io_o> is being overridden by the user with net <net_reset_sel_axi_mm_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axi_mm/gpio_io_i> is being overridden by the user with net <net_reset_sel_axi_mm_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_o> is being overridden by the user with net <net_reset_sel_axis_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_i> is being overridden by the user with net <net_reset_sel_axis_gpio_io_o>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </deint_ss/m_axis_tuser> is being overridden by the user with net <net_deint_ss_m_axis_tuser>. This pin will not be connected as a part of interface connection <M_AXIS>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </deint_cc/s_axis_tuser> is being overridden by the user with net <net_deint_concat_dout>. This pin will not be connected as a part of interface connection <S_AXIS>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </deint_cc/m_axis_tuser> is being overridden by the user with net <net_deint_cc_m_axis_tuser>. This pin will not be connected as a part of interface connection <M_AXIS>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </dint/s_axis_video_TUSER> is being overridden by the user with net <net_deint_tuser_tap_Dout>. This pin will not be connected as a part of interface connection <s_axis_video>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
1
true
true
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
Slave segment '/axi_vdma/S_AXI_LITE/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0000_0000 [ 64K ]>.
Slave segment '/csc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0001_0000 [ 64K ]>.
Slave segment '/dint/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0002_0000 [ 64K ]>.
Slave segment '/hcr/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0003_0000 [ 64K ]>.
Slave segment '/hsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0004_0000 [ 64K ]>.
Slave segment '/ltr/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0005_0000 [ 64K ]>.
Slave segment '/reset_sel_axi_mm/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0006_0000 [ 64K ]>.
Slave segment '/reset_sel_axis/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0007_0000 [ 64K ]>.
Slave segment '/vcr_i/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0008_0000 [ 64K ]>.
Slave segment '/vcr_o/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0009_0000 [ 64K ]>.
Slave segment '/video_router/xbar/S_AXI_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x000A_0000 [ 64K ]>.
Slave segment '/vsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x000B_0000 [ 64K ]>.
m_axi_mm_width = 64
m_axi_mm_width = 64
m_axi_mm_width = 64
m_axi_mm_width = 64
m_axi_mm_width = 64
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_i> is being overridden by the user with net <net_reset_sel_axis_gpio_io_i>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </reset_sel_axis/gpio_io_o> is being overridden by the user with net <net_reset_sel_axis_gpio_io_i>. This pin will not be connected as a part of interface connection <GPIO>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
0
true
true
INFO: [BD 41-3093] Triggering Legacy Auto Assign Algorithm
Slave segment '/hsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0000_0000 [ 64K ]>.
Slave segment '/reset_sel_axis/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0001_0000 [ 64K ]>.
Slave segment '/vsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0002_0000 [ 64K ]>.
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [xilinx.com:ip:vcu:1.2-17] /vcu/vcu_0: Init
WARNING: [IP_Flow 19-4684] Expected long value for param ENC_BUFFER_SIZE_ACTUAL but, float/scientific notation value 284.533935546875 is provided. The value is converted to long type(284)
WARNING: [IP_Flow 19-4684] Expected long value for param ENC_BUFFER_SIZE but, float/scientific notation value 253.0301513671875 is provided. The value is converted to long type(253)
WARNING: [IP_Flow 19-4684] Expected long value for param ENC_BUFFER_SIZE_ACTUAL but, float/scientific notation value 284.533935546875 is provided. The value is converted to long type(284)
WARNING: [IP_Flow 19-4684] Expected long value for param ENC_BUFFER_SIZE but, float/scientific notation value 253.0301513671875 is provided. The value is converted to long type(253)
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilconcat:1.0 for the IP type xilinx.com:ip:xlconcat:2.1 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlconcat:2.1 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilconcat:1.0 for the IP type xilinx.com:ip:xlconcat:2.1 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlconcat:2.1 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994
WARNING: [BD 41-1306] The connection to interface pin </PS_0/emio_gpio_o> is being overridden by the user with net <PS_0_emio_gpio_o>. This pin will not be connected as a part of interface connection <GPIO_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
Slave segment '/axi_gpio_0/S_AXI/Reg' is being assigned into address space '/PS_0/Data' at <0x8008_0000 [ 64K ]>.
Slave segment '/axi_gpio_1/S_AXI/Reg' is being assigned into address space '/PS_0/Data' at <0x8002_0000 [ 64K ]>.
Slave segment '/axi_iic_0/S_AXI/Reg' is being assigned into address space '/PS_0/Data' at <0x8003_0000 [ 64K ]>.
Slave segment '/capture_pipeline_isp/mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg' is being assigned into address space '/PS_0/Data' at <0x8000_0000 [ 64K ]>.
Slave segment '/capture_pipeline_ias/mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg' is being assigned into address space '/PS_0/Data' at <0x8001_0000 [ 64K ]>.
Slave segment '/capture_pipeline_raspi/mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg' is being assigned into address space '/PS_0/Data' at <0x8005_0000 [ 64K ]>.
Slave segment '/capture_pipeline_ias/v_demosaic_0/s_axi_CTRL/Reg' is being assigned into address space '/PS_0/Data' at <0xB000_0000 [ 64K ]>.
Slave segment '/capture_pipeline_raspi/v_demosaic_0/s_axi_CTRL/Reg' is being assigned into address space '/PS_0/Data' at <0xB003_0000 [ 64K ]>.
Slave segment '/capture_pipeline_isp/v_frmbuf_wr_0/s_axi_CTRL/Reg' is being assigned into address space '/PS_0/Data' at <0xB001_0000 [ 64K ]>.
Slave segment '/capture_pipeline_ias/v_frmbuf_wr_0/s_axi_CTRL/Reg' is being assigned into address space '/PS_0/Data' at <0xB002_0000 [ 64K ]>.
Slave segment '/capture_pipeline_raspi/v_frmbuf_wr_0/s_axi_CTRL/Reg' is being assigned into address space '/PS_0/Data' at <0xB00C_0000 [ 64K ]>.
Slave segment '/capture_pipeline_ias/v_proc_ss_0/s_axi_ctrl/Reg' is being assigned into address space '/PS_0/Data' at <0xB004_0000 [ 256K ]>.
Slave segment '/capture_pipeline_raspi/v_proc_ss_0/s_axi_ctrl/Reg' is being assigned into address space '/PS_0/Data' at <0xB008_0000 [ 256K ]>.
Slave segment '/vcu/vcu_0/S_AXI_LITE/Reg' is being assigned into address space '/PS_0/Data' at <0x8010_0000 [ 1M ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/capture_pipeline_ias/v_frmbuf_wr_0/Data_m_axi_mm_video' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_QSPI' is being assigned into address space '/capture_pipeline_ias/v_frmbuf_wr_0/Data_m_axi_mm_video' at <0xC000_0000 [ 512M ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/capture_pipeline_isp/v_frmbuf_wr_0/Data_m_axi_mm_video' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_QSPI' is being assigned into address space '/capture_pipeline_isp/v_frmbuf_wr_0/Data_m_axi_mm_video' at <0xC000_0000 [ 512M ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/capture_pipeline_raspi/v_frmbuf_wr_0/Data_m_axi_mm_video' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_QSPI' is being assigned into address space '/capture_pipeline_raspi/v_frmbuf_wr_0/Data_m_axi_mm_video' at <0xC000_0000 [ 512M ]>.
Slave segment '/PS_0/SAXIGP6/LPD_DDR_HIGH' is being assigned into address space '/vcu/vcu_0/Code' at <0x8_0000_0000 [ 32G ]>.
Slave segment '/PS_0/SAXIGP6/LPD_DDR_LOW' is being assigned into address space '/vcu/vcu_0/Code' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP6/LPD_LPS_OCM' is being assigned into address space '/vcu/vcu_0/Code' at <0xFF00_0000 [ 16M ]>.
Slave segment '/PS_0/SAXIGP6/LPD_QSPI' is being assigned into address space '/vcu/vcu_0/Code' at <0xC000_0000 [ 512M ]>.
Slave segment '/PS_0/SAXIGP4/HP2_DDR_HIGH' is being assigned into address space '/vcu/vcu_0/DecData0' at <0x8_0000_0000 [ 32G ]>.
Slave segment '/PS_0/SAXIGP4/HP2_DDR_LOW' is being assigned into address space '/vcu/vcu_0/DecData0' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP4/HP2_LPS_OCM' is being assigned into address space '/vcu/vcu_0/DecData0' at <0xFF00_0000 [ 16M ]>.
Slave segment '/PS_0/SAXIGP4/HP2_QSPI' is being assigned into address space '/vcu/vcu_0/DecData0' at <0xC000_0000 [ 512M ]>.
Slave segment '/PS_0/SAXIGP4/HP2_DDR_HIGH' is being assigned into address space '/vcu/vcu_0/DecData1' at <0x8_0000_0000 [ 32G ]>.
Slave segment '/PS_0/SAXIGP4/HP2_DDR_LOW' is being assigned into address space '/vcu/vcu_0/DecData1' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP4/HP2_LPS_OCM' is being assigned into address space '/vcu/vcu_0/DecData1' at <0xFF00_0000 [ 16M ]>.
Slave segment '/PS_0/SAXIGP4/HP2_QSPI' is being assigned into address space '/vcu/vcu_0/DecData1' at <0xC000_0000 [ 512M ]>.
Slave segment '/PS_0/SAXIGP3/HP1_DDR_HIGH' is being assigned into address space '/vcu/vcu_0/EncData0' at <0x8_0000_0000 [ 32G ]>.
Slave segment '/PS_0/SAXIGP3/HP1_DDR_LOW' is being assigned into address space '/vcu/vcu_0/EncData0' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP3/HP1_LPS_OCM' is being assigned into address space '/vcu/vcu_0/EncData0' at <0xFF00_0000 [ 16M ]>.
Slave segment '/PS_0/SAXIGP3/HP1_QSPI' is being assigned into address space '/vcu/vcu_0/EncData0' at <0xC000_0000 [ 512M ]>.
Slave segment '/PS_0/SAXIGP3/HP1_DDR_HIGH' is being assigned into address space '/vcu/vcu_0/EncData1' at <0x8_0000_0000 [ 32G ]>.
Slave segment '/PS_0/SAXIGP3/HP1_DDR_LOW' is being assigned into address space '/vcu/vcu_0/EncData1' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP3/HP1_LPS_OCM' is being assigned into address space '/vcu/vcu_0/EncData1' at <0xFF00_0000 [ 16M ]>.
Slave segment '/PS_0/SAXIGP3/HP1_QSPI' is being assigned into address space '/vcu/vcu_0/EncData1' at <0xC000_0000 [ 512M ]>.
WARNING: [BD 41-2670] Found an incomplete address path from address space '/PS_0/Data' to master interface '/PS_0/M_AXI_HPM0_FPD'. Please either complete or remove this path to resolve.
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter M_TDATA_NUM_BYTES(2) on '/capture_pipeline_ias/axis_subset_converter_0' with propagated value(3). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter M_TDEST_WIDTH(1) on '/capture_pipeline_ias/axis_subset_converter_0' with propagated value(0). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter M_TDATA_NUM_BYTES(6) on '/capture_pipeline_isp/axis_subset_converter_0' with propagated value(4). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter M_TDEST_WIDTH(1) on '/capture_pipeline_isp/axis_subset_converter_0' with propagated value(10). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter M_TDATA_NUM_BYTES(1) on '/capture_pipeline_raspi/axis_subset_converter_0' with propagated value(2). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter M_TDEST_WIDTH(1) on '/capture_pipeline_raspi/axis_subset_converter_0' with propagated value(0). Command ignored
WARNING: [IP_Flow 19-4684] Expected long value for param HDL_PLL_CLK_LO but, float/scientific notation value 0.0 is provided. The value is converted to long type(0)
WARNING: [IP_Flow 19-4684] Expected long value for param HDL_PLL_CLK_HI but, float/scientific notation value 50.0 is provided. The value is converted to long type(50)
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_bist_vcu_0_0: in flao2hex update method .. 0.0
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_bist_vcu_0_0: in HDL_AXI_ENC_CLK update method ..0
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_bist_vcu_0_0: in HDL_AXI_DEC_CLK update method ..0
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_bist_vcu_0_0: in flao2hex update method .. 3.0
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_bist_vcu_0_0: in HDL_AXI_MCU_CLK update method ..1077936128
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_bist_vcu_0_0: in flao2hex update method .. 2.99
INFO: [xilinx.com:ip:vcu:1.2-603] kv260_bist_vcu_0_0: in HDL_AXI_MCU_CLK update method ..1077894184
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter M_TDEST_WIDTH(1) on '/capture_pipeline_ias/axis_subset_converter_0' with propagated value(10). Command ignored
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter M_TDEST_WIDTH(1) on '/capture_pipeline_raspi/axis_subset_converter_0' with propagated value(10). Command ignored
INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0002_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M01_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0001_0000 [ 64K ]> from slave interface '/smartconnect_0/S00_AXI' to master interface '/smartconnect_0/M02_AXI'. This will be used by smartconnect on path for routing.
INFO: [xilinx.com:ip:smartconnect:1.0-1] bd_cb21_smartconnect_0_0: SmartConnect bd_cb21_smartconnect_0_0 is in Low-Area Mode.
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [xilinx.com:ip:smartconnect:1.0-1] bd_0be0_smartconnect_0_0: SmartConnect bd_0be0_smartconnect_0_0 is in Low-Area Mode.
INFO: [xilinx.com:ip:vcu:1.2-17] /vcu/vcu_0:Pre-Propagate .
INFO: [xilinx.com:ip:vcu:1.2-17] /vcu/vcu_0: Post Propogate .
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect_ctrl_300/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect_ctrl_300/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect_ctrl_100/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM0_LPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect_ctrl_100/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM0_LPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /PS_0/S_AXI_LPD(1) and /vcu/axi_interconnect_0/s00_couplers/auto_us/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /PS_0/S_AXI_LPD(1) and /vcu/axi_interconnect_0/s00_couplers/auto_us/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /PS_0/S_AXI_HP1_FPD(1) and /vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /PS_0/S_AXI_HP1_FPD(1) and /vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /PS_0/S_AXI_HP2_FPD(1) and /vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /PS_0/S_AXI_HP2_FPD(1) and /vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/M_AXI(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /PS_0/S_AXI_HP0_FPD(1) and /axi_interconnect_cap/xbar/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /PS_0/S_AXI_HP0_FPD(1) and /axi_interconnect_cap/xbar/M00_AXI(0)
validate_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2856.047 ; gain = 15.844 ; free physical = 50307 ; free virtual = 72833
Wrote : </media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.srcs/sources_1/bd/kv260_bist/kv260_bist.bd>
INFO: [BD 41-1662] The design 'kv260_bist.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/m_axi_rid'(5) to pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/m_axi_bid'(5) to pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/m_axi_rid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/m_axi_bid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_interconnect_cap/xbar/m_axi_bid'(2) to pin: '/axi_interconnect_cap/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_interconnect_cap/xbar/m_axi_rid'(2) to pin: '/axi_interconnect_cap/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_awid'(6) to pin: '/axi_interconnect_cap/M00_AXI_awid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_arid'(6) to pin: '/axi_interconnect_cap/M00_AXI_arid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp4_awid'(6) to pin: '/vcu/M00_AXI_VCU_DEC_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp4_arid'(6) to pin: '/vcu/M00_AXI_VCU_DEC_arid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp3_awid'(6) to pin: '/vcu/M00_AXI_VCU_EN_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp3_arid'(6) to pin: '/vcu/M00_AXI_VCU_EN_arid'(5) - Only lower order bits will be connected.
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/m_axi_rid'(5) to pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/m_axi_bid'(5) to pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/m_axi_rid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/m_axi_bid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_interconnect_cap/xbar/m_axi_bid'(2) to pin: '/axi_interconnect_cap/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_interconnect_cap/xbar/m_axi_rid'(2) to pin: '/axi_interconnect_cap/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_awid'(6) to pin: '/axi_interconnect_cap/M00_AXI_awid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_arid'(6) to pin: '/axi_interconnect_cap/M00_AXI_arid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp4_awid'(6) to pin: '/vcu/M00_AXI_VCU_DEC_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp4_arid'(6) to pin: '/vcu/M00_AXI_VCU_DEC_arid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp3_awid'(6) to pin: '/vcu/M00_AXI_VCU_EN_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp3_arid'(6) to pin: '/vcu/M00_AXI_VCU_EN_arid'(5) - Only lower order bits will be connected.
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/sim/kv260_bist.v
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/hdl/kv260_bist_wrapper.v
INFO: [Project 1-1716] Could not find the wrapper file ./project/kv260_bist.srcs/sources_1/bd/kv260_bist/hdl/kv260_bist_wrapper.v, checking in project .gen location instead.
INFO: [Vivado 12-12391] Found file ./project/kv260_bist.gen/sources_1/bd/kv260_bist/hdl/kv260_bist_wrapper.v, importing it to Project
INFO: [BD 5-320] Validate design is not run, since the design is already validated.
INFO: [BD 41-1662] The design 'kv260_bist.bd' is already validated. Therefore parameter propagation will not be re-run.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/m_axi_rid'(5) to pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/m_axi_bid'(5) to pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/m_axi_rid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/m_axi_bid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_interconnect_cap/xbar/m_axi_bid'(2) to pin: '/axi_interconnect_cap/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_interconnect_cap/xbar/m_axi_rid'(2) to pin: '/axi_interconnect_cap/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_awid'(6) to pin: '/axi_interconnect_cap/M00_AXI_awid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_arid'(6) to pin: '/axi_interconnect_cap/M00_AXI_arid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp4_awid'(6) to pin: '/vcu/M00_AXI_VCU_DEC_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp4_arid'(6) to pin: '/vcu/M00_AXI_VCU_DEC_arid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp3_awid'(6) to pin: '/vcu/M00_AXI_VCU_EN_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp3_arid'(6) to pin: '/vcu/M00_AXI_VCU_EN_arid'(5) - Only lower order bits will be connected.
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/m_axi_rid'(5) to pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice/m_axi_bid'(5) to pin: '/vcu/axi_interconnect_vcu_en/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_en/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_en/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice/m_axi_rid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_rid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice/m_axi_bid'(4) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_bid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/m_axi_rid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice/m_axi_bid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s00_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_awid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_awid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/vcu/axi_interconnect_vcu_dec/xbar/s_axi_arid'(5) to pin: '/vcu/axi_interconnect_vcu_dec/s01_couplers/M_AXI_arid'(4) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_interconnect_cap/xbar/m_axi_bid'(2) to pin: '/axi_interconnect_cap/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_interconnect_cap/xbar/m_axi_rid'(2) to pin: '/axi_interconnect_cap/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_awid'(6) to pin: '/axi_interconnect_cap/M00_AXI_awid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp2_arid'(6) to pin: '/axi_interconnect_cap/M00_AXI_arid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp4_awid'(6) to pin: '/vcu/M00_AXI_VCU_DEC_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp4_arid'(6) to pin: '/vcu/M00_AXI_VCU_DEC_arid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp3_awid'(6) to pin: '/vcu/M00_AXI_VCU_EN_awid'(5) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/PS_0/saxigp3_arid'(6) to pin: '/vcu/M00_AXI_VCU_EN_arid'(5) - Only lower order bits will be connected.
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/sim/kv260_bist.v
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/hdl/kv260_bist_wrapper.v
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.5-0] kv260_bist_PS_0_0:
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Amd's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Amd's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM1_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_LPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HPC0_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HPC1_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP1_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP2_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP3_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_LPD'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block PS_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_iic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_ctrl_100/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0/kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_ctrl_100/s00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_ctrl_300/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0/kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_ctrl_300/s00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/axis_data_fifo_cap .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_axis_subset_converter_0_0/kv260_bist_axis_subset_converter_0_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/axis_subset_converter_0 .
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M00_AXIS.TDATA_NUM_BYTES'. Logical port width '8' and physical port width '32' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M00_AXIS.TUSER_WIDTH'. Logical port width '96' and physical port width '384' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M00_AXIS.TDEST_WIDTH'. Logical port width '4' and physical port width '16' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M01_AXIS.TDATA_NUM_BYTES'. Logical port width '8' and physical port width '32' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M01_AXIS.TUSER_WIDTH'. Logical port width '96' and physical port width '384' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M01_AXIS.TDEST_WIDTH'. Logical port width '4' and physical port width '16' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M02_AXIS.TDATA_NUM_BYTES'. Logical port width '8' and physical port width '32' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M02_AXIS.TUSER_WIDTH'. Logical port width '96' and physical port width '384' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M02_AXIS.TDEST_WIDTH'. Logical port width '4' and physical port width '16' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M03_AXIS.TDATA_NUM_BYTES'. Logical port width '8' and physical port width '32' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M03_AXIS.TUSER_WIDTH'. Logical port width '96' and physical port width '384' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M03_AXIS.TDEST_WIDTH'. Logical port width '4' and physical port width '16' do not match.
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_mipi_csi2_rx_subsyst_0_0/bd_0/hw_handoff/kv260_bist_mipi_csi2_rx_subsyst_0_0.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_mipi_csi2_rx_subsyst_0_0/bd_0/synth/kv260_bist_mipi_csi2_rx_subsyst_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/mipi_csi2_rx_subsyst_0 .
WARNING: [IP_Flow 19-1971] File named "sim/kv260_bist_v_demosaic_0_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/v_demosaic_0 .
WARNING: [IP_Flow 19-1971] File named "sim/kv260_bist_v_frmbuf_wr_0_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/v_frmbuf_wr_0 .
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_0/bd_1/hw_handoff/bd_cb21_smartconnect_0_0.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_0/bd_1/synth/bd_cb21_smartconnect_0_0.hwdef
WARNING: [IP_Flow 19-1971] File named "sim/bd_cb21_vsc_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "sim/bd_cb21_hsc_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_0/bd_0/ip/ip_3/bd_cb21_input_size_set_0_ooc.xdc'
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_0/bd_0/hw_handoff/kv260_bist_v_proc_ss_0_0.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_0/bd_0/synth/kv260_bist_v_proc_ss_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/v_proc_ss_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/xlslice_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/xlslice_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_ias/xlslice_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_isp/axis_data_fifo_cap .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_axis_subset_converter_0_1/kv260_bist_axis_subset_converter_0_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_isp/axis_subset_converter_0 .
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_mipi_csi2_rx_subsyst_0_1/bd_0/hw_handoff/kv260_bist_mipi_csi2_rx_subsyst_0_1.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_mipi_csi2_rx_subsyst_0_1/bd_0/synth/kv260_bist_mipi_csi2_rx_subsyst_0_1.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_isp/mipi_csi2_rx_subsyst_0 .
WARNING: [IP_Flow 19-1971] File named "sim/kv260_bist_v_frmbuf_wr_0_1.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_isp/v_frmbuf_wr_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_isp/xlslice_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/axis_data_fifo_cap .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_axis_subset_converter_0_2/kv260_bist_axis_subset_converter_0_2_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/axis_subset_converter_0 .
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M00_AXIS.TDATA_NUM_BYTES'. Logical port width '8' and physical port width '32' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M00_AXIS.TUSER_WIDTH'. Logical port width '96' and physical port width '384' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M00_AXIS.TDEST_WIDTH'. Logical port width '4' and physical port width '16' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M01_AXIS.TDATA_NUM_BYTES'. Logical port width '8' and physical port width '32' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M01_AXIS.TUSER_WIDTH'. Logical port width '96' and physical port width '384' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M01_AXIS.TDEST_WIDTH'. Logical port width '4' and physical port width '16' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M02_AXIS.TDATA_NUM_BYTES'. Logical port width '8' and physical port width '32' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M02_AXIS.TUSER_WIDTH'. Logical port width '96' and physical port width '384' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M02_AXIS.TDEST_WIDTH'. Logical port width '4' and physical port width '16' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M03_AXIS.TDATA_NUM_BYTES'. Logical port width '8' and physical port width '32' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M03_AXIS.TUSER_WIDTH'. Logical port width '96' and physical port width '384' do not match.
WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M03_AXIS.TDEST_WIDTH'. Logical port width '4' and physical port width '16' do not match.
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_mipi_csi2_rx_subsyst_0_2/bd_0/hw_handoff/kv260_bist_mipi_csi2_rx_subsyst_0_2.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_mipi_csi2_rx_subsyst_0_2/bd_0/synth/kv260_bist_mipi_csi2_rx_subsyst_0_2.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/mipi_csi2_rx_subsyst_0 .
WARNING: [IP_Flow 19-1971] File named "sim/kv260_bist_v_demosaic_0_1.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/v_demosaic_0 .
WARNING: [IP_Flow 19-1971] File named "sim/kv260_bist_v_frmbuf_wr_0_2.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/v_frmbuf_wr_0 .
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_1/bd_1/hw_handoff/bd_0be0_smartconnect_0_0.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_1/bd_1/synth/bd_0be0_smartconnect_0_0.hwdef
WARNING: [IP_Flow 19-1971] File named "sim/bd_0be0_vsc_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "sim/bd_0be0_hsc_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_1/bd_0/ip/ip_3/bd_0be0_input_size_set_0_ooc.xdc'
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_1/bd_0/hw_handoff/kv260_bist_v_proc_ss_0_1.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_v_proc_ss_0_1/bd_0/synth/kv260_bist_v_proc_ss_0_1.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/v_proc_ss_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/xlslice_4 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/xlslice_5 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block capture_pipeline_raspi/xlslice_6 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_100MHz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_300MHz .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_axi_interconnect_0_imp_auto_us_0/kv260_bist_axi_interconnect_0_imp_auto_us_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_0/s00_couplers/auto_us .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_register_slice_0 .
FAMILY is zynquplus
DEVICE is xck26
PACKAGE is sfvc784
SPEEDGRADE is -2LV
SILICON_REVISION is
TEMPERATURE_GRADE is C
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/vcu_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_en/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_en/s00_couplers/s00_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_en/s01_couplers/s01_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_en/m00_couplers/m00_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_dec/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_dec/s00_couplers/s00_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_dec/s01_couplers/s01_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block vcu/axi_interconnect_vcu_dec/m00_couplers/m00_regslice .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_irq0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_irq1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlslice_7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlslice_fan .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_cap/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_axi_interconnect_cap_imp_auto_us_0/kv260_bist_axi_interconnect_cap_imp_auto_us_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_cap/s02_couplers/auto_us .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_cap/s00_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_cap/s01_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_cap/s02_mmu .
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/hw_handoff/kv260_bist.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.hwdef
generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 3367.848 ; gain = 0.000 ; free physical = 50037 ; free virtual = 72738
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Sun Jul 13 13:45:15 2025] Launched kv260_bist_axi_interconnect_vcu_en_imp_m00_regslice_0_synth_1, kv260_bist_axi_interconnect_vcu_en_imp_s01_regslice_0_synth_1, kv260_bist_axi_interconnect_vcu_en_imp_s00_regslice_0_synth_1, bd_0be0_rst_axis_0_synth_1, bd_cb21_axis_fifo_0_synth_1, bd_cb21_axis_register_slice_0_0_synth_1, kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0_synth_1, kv260_bist_axi_interconnect_vcu_dec_imp_xbar_0_synth_1, kv260_bist_axi_interconnect_cap_imp_s00_mmu_0_synth_1, bd_0be0_input_size_set_0_synth_1, bd_cb21_input_size_set_0_synth_1, bd_0be0_smartconnect_0_0_synth_1, bd_970d_phy_0_synth_1, bd_0be0_axis_register_slice_0_0_synth_1, bd_0be0_vsc_0_synth_1, bd_0be0_axis_fifo_0_synth_1, bd_970d_vfb_0_0_synth_1, kv260_bist_axi_register_slice_0_0_synth_1, bd_970d_rx_0_synth_1, bd_964d_phy_0_synth_1, bd_cb21_rst_axis_0_synth_1, bd_cb21_hsc_0_synth_1, bd_cb21_reset_sel_axis_0_synth_1, bd_cb21_vsc_0_synth_1, kv260_bist_axis_subset_converter_0_1_synth_1, kv260_bist_axis_data_fifo_cap_1_synth_1, kv260_bist_proc_sys_reset_100MHz_0_synth_1, kv260_bist_proc_sys_reset_300MHz_0_synth_1, kv260_bist_clk_wiz_0_0_synth_1, kv260_bist_mipi_csi2_rx_subsyst_0_2_synth_1, kv260_bist_axi_interconnect_0_imp_auto_us_0_synth_1, bd_964d_vfb_0_0_synth_1, bd_964d_rx_0_synth_1, kv260_bist_axis_subset_converter_0_2_synth_1, bd_964d_r_sync_0_synth_1, kv260_bist_v_demosaic_0_1_synth_1, kv260_bist_v_frmbuf_wr_0_1_synth_1, kv260_bist_axis_data_fifo_cap_2_synth_1, kv260_bist_v_proc_ss_0_1_synth_1, bd_970d_r_sync_0_synth_1, kv260_bist_axis_subset_converter_0_0_synth_1, kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0_synth_1, kv260_bist_v_demosaic_0_0_synth_1, kv260_bist_axi_interconnect_cap_imp_auto_us_0_synth_1, bd_568c_r_sync_0_synth_1, kv260_bist_axi_interconnect_vcu_dec_imp_m00_regslice_0_synth_1, kv260_bist_v_frmbuf_wr_0_0_synth_1, kv260_bist_axi_interconnect_vcu_dec_imp_s01_regslice_0_synth_1, kv260_bist_mipi_csi2_rx_subsyst_0_0_synth_1, kv260_bist_v_proc_ss_0_0_synth_1, kv260_bist_axis_data_fifo_cap_0_synth_1, kv260_bist_axi_interconnect_vcu_dec_imp_s00_regslice_0_synth_1, kv260_bist_axi_interconnect_ctrl_300_imp_xbar_0_synth_1, kv260_bist_axi_gpio_1_0_synth_1, kv260_bist_axi_gpio_0_0_synth_1, kv260_bist_axi_iic_0_0_synth_1, kv260_bist_PS_0_0_synth_1, kv260_bist_axi_interconnect_cap_imp_s02_mmu_0_synth_1, kv260_bist_axi_interconnect_cap_imp_s01_mmu_0_synth_1, bd_568c_rx_0_synth_1, bd_568c_vfb_0_0_synth_1, bd_568c_phy_0_synth_1, bd_cb21_smartconnect_0_0_synth_1, kv260_bist_axi_interconnect_cap_imp_xbar_0_synth_1, kv260_bist_axi_interconnect_vcu_en_imp_xbar_0_synth_1, bd_0be0_hsc_0_synth_1, kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0_synth_1, bd_0be0_reset_sel_axis_0_synth_1, kv260_bist_mipi_csi2_rx_subsyst_0_1_synth_1, kv260_bist_v_frmbuf_wr_0_2_synth_1, kv260_bist_vcu_0_0_synth_1...
Run output will be captured here:
kv260_bist_axi_interconnect_vcu_en_imp_m00_regslice_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_vcu_en_imp_m00_regslice_0_synth_1/runme.log
kv260_bist_axi_interconnect_vcu_en_imp_s01_regslice_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_vcu_en_imp_s01_regslice_0_synth_1/runme.log
kv260_bist_axi_interconnect_vcu_en_imp_s00_regslice_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_vcu_en_imp_s00_regslice_0_synth_1/runme.log
bd_0be0_rst_axis_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_0be0_rst_axis_0_synth_1/runme.log
bd_cb21_axis_fifo_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_cb21_axis_fifo_0_synth_1/runme.log
bd_cb21_axis_register_slice_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_cb21_axis_register_slice_0_0_synth_1/runme.log
kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0_synth_1/runme.log
kv260_bist_axi_interconnect_vcu_dec_imp_xbar_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_vcu_dec_imp_xbar_0_synth_1/runme.log
kv260_bist_axi_interconnect_cap_imp_s00_mmu_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_cap_imp_s00_mmu_0_synth_1/runme.log
bd_0be0_input_size_set_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_0be0_input_size_set_0_synth_1/runme.log
bd_cb21_input_size_set_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_cb21_input_size_set_0_synth_1/runme.log
bd_0be0_smartconnect_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_0be0_smartconnect_0_0_synth_1/runme.log
bd_970d_phy_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_970d_phy_0_synth_1/runme.log
bd_0be0_axis_register_slice_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_0be0_axis_register_slice_0_0_synth_1/runme.log
bd_0be0_vsc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_0be0_vsc_0_synth_1/runme.log
bd_0be0_axis_fifo_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_0be0_axis_fifo_0_synth_1/runme.log
bd_970d_vfb_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_970d_vfb_0_0_synth_1/runme.log
kv260_bist_axi_register_slice_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_register_slice_0_0_synth_1/runme.log
bd_970d_rx_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_970d_rx_0_synth_1/runme.log
bd_964d_phy_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_964d_phy_0_synth_1/runme.log
bd_cb21_rst_axis_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_cb21_rst_axis_0_synth_1/runme.log
bd_cb21_hsc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_cb21_hsc_0_synth_1/runme.log
bd_cb21_reset_sel_axis_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_cb21_reset_sel_axis_0_synth_1/runme.log
bd_cb21_vsc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_cb21_vsc_0_synth_1/runme.log
kv260_bist_axis_subset_converter_0_1_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axis_subset_converter_0_1_synth_1/runme.log
kv260_bist_axis_data_fifo_cap_1_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axis_data_fifo_cap_1_synth_1/runme.log
kv260_bist_proc_sys_reset_100MHz_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_proc_sys_reset_100MHz_0_synth_1/runme.log
kv260_bist_proc_sys_reset_300MHz_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_proc_sys_reset_300MHz_0_synth_1/runme.log
kv260_bist_clk_wiz_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_clk_wiz_0_0_synth_1/runme.log
kv260_bist_mipi_csi2_rx_subsyst_0_2_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_mipi_csi2_rx_subsyst_0_2_synth_1/runme.log
kv260_bist_axi_interconnect_0_imp_auto_us_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_0_imp_auto_us_0_synth_1/runme.log
bd_964d_vfb_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_964d_vfb_0_0_synth_1/runme.log
bd_964d_rx_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_964d_rx_0_synth_1/runme.log
kv260_bist_axis_subset_converter_0_2_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axis_subset_converter_0_2_synth_1/runme.log
bd_964d_r_sync_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_964d_r_sync_0_synth_1/runme.log
kv260_bist_v_demosaic_0_1_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_v_demosaic_0_1_synth_1/runme.log
kv260_bist_v_frmbuf_wr_0_1_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_v_frmbuf_wr_0_1_synth_1/runme.log
kv260_bist_axis_data_fifo_cap_2_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axis_data_fifo_cap_2_synth_1/runme.log
kv260_bist_v_proc_ss_0_1_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_v_proc_ss_0_1_synth_1/runme.log
bd_970d_r_sync_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_970d_r_sync_0_synth_1/runme.log
kv260_bist_axis_subset_converter_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axis_subset_converter_0_0_synth_1/runme.log
kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0_synth_1/runme.log
kv260_bist_v_demosaic_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_v_demosaic_0_0_synth_1/runme.log
kv260_bist_axi_interconnect_cap_imp_auto_us_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_cap_imp_auto_us_0_synth_1/runme.log
bd_568c_r_sync_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_568c_r_sync_0_synth_1/runme.log
kv260_bist_axi_interconnect_vcu_dec_imp_m00_regslice_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_vcu_dec_imp_m00_regslice_0_synth_1/runme.log
kv260_bist_v_frmbuf_wr_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_v_frmbuf_wr_0_0_synth_1/runme.log
kv260_bist_axi_interconnect_vcu_dec_imp_s01_regslice_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_vcu_dec_imp_s01_regslice_0_synth_1/runme.log
kv260_bist_mipi_csi2_rx_subsyst_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_mipi_csi2_rx_subsyst_0_0_synth_1/runme.log
kv260_bist_v_proc_ss_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_v_proc_ss_0_0_synth_1/runme.log
kv260_bist_axis_data_fifo_cap_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axis_data_fifo_cap_0_synth_1/runme.log
kv260_bist_axi_interconnect_vcu_dec_imp_s00_regslice_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_vcu_dec_imp_s00_regslice_0_synth_1/runme.log
kv260_bist_axi_interconnect_ctrl_300_imp_xbar_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_ctrl_300_imp_xbar_0_synth_1/runme.log
kv260_bist_axi_gpio_1_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_gpio_1_0_synth_1/runme.log
kv260_bist_axi_gpio_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_gpio_0_0_synth_1/runme.log
kv260_bist_axi_iic_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_iic_0_0_synth_1/runme.log
kv260_bist_PS_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_PS_0_0_synth_1/runme.log
kv260_bist_axi_interconnect_cap_imp_s02_mmu_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_cap_imp_s02_mmu_0_synth_1/runme.log
kv260_bist_axi_interconnect_cap_imp_s01_mmu_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_cap_imp_s01_mmu_0_synth_1/runme.log
bd_568c_rx_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_568c_rx_0_synth_1/runme.log
bd_568c_vfb_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_568c_vfb_0_0_synth_1/runme.log
bd_568c_phy_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_568c_phy_0_synth_1/runme.log
bd_cb21_smartconnect_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_cb21_smartconnect_0_0_synth_1/runme.log
kv260_bist_axi_interconnect_cap_imp_xbar_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_cap_imp_xbar_0_synth_1/runme.log
kv260_bist_axi_interconnect_vcu_en_imp_xbar_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_vcu_en_imp_xbar_0_synth_1/runme.log
bd_0be0_hsc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_0be0_hsc_0_synth_1/runme.log
kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0_synth_1/runme.log
bd_0be0_reset_sel_axis_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/bd_0be0_reset_sel_axis_0_synth_1/runme.log
kv260_bist_mipi_csi2_rx_subsyst_0_1_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_mipi_csi2_rx_subsyst_0_1_synth_1/runme.log
kv260_bist_v_frmbuf_wr_0_2_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_v_frmbuf_wr_0_2_synth_1/runme.log
kv260_bist_vcu_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/kv260_bist_vcu_0_0_synth_1/runme.log
[Sun Jul 13 13:45:15 2025] Launched synth_1...
Run output will be captured here: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/runme.log
[Sun Jul 13 13:45:15 2025] Waiting for synth_1 to finish...
*** Running vivado
with args -log kv260_bist_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source kv260_bist_wrapper.tcl
****** Vivado v2025.1 (64-bit)
**** SW Build 6140274 on Wed May 21 22:58:25 MDT 2025
**** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025
**** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025
**** Start of session at: Sun Jul 13 13:51:33 2025
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
source kv260_bist_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/ip'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.1/Vivado/data/ip'.
INFO: [Project 1-5698] Found the below utility IPs instantiated in block design /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.srcs/sources_1/bd/kv260_bist/kv260_bist.bd which have equivalent inline hdl with improved performance and reduced diskspace.
It is recommended to migrate these utility IPs to inline hdl using the command upgrade_project -migrate_to_inline_hdl. The utility IPs may be deprecated in future releases.
More information on inline hdl is available in UG994.
Utility IP Component Instances:
kv260_bist_xlslice_1_0
kv260_bist_xlslice_2_0
kv260_bist_xlslice_3_0
kv260_bist_xlslice_0_0
kv260_bist_xlslice_4_0
kv260_bist_xlslice_5_0
kv260_bist_xlslice_6_0
kv260_bist_xlconcat_irq0_0
kv260_bist_xlconcat_irq1_0
kv260_bist_xlslice_7_0
kv260_bist_xlslice_fan_0
Command: synth_design -top kv260_bist_wrapper -part xck26-sfvc784-2LV-c
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xck26'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xck26'
INFO: [Device 21-403] Loading part xck26-sfvc784-2LV-c
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 110759
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2819.656 ; gain = 140.859 ; free physical = 46528 ; free virtual = 70372
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_wrapper' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.srcs/sources_1/imports/hdl/kv260_bist_wrapper.v:13]
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/tools/Xilinx/2025.1/Vivado/scripts/rt/data/unisim_comp.v:81434]
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/tools/Xilinx/2025.1/Vivado/scripts/rt/data/unisim_comp.v:81434]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1642]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_PS_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_PS_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_PS_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_PS_0_0_stub.v:6]
WARNING: [Synth 8-7071] port 'maxigp0_awid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awaddr' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awlen' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awsize' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awburst' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awlock' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awcache' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awprot' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awuser' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_wdata' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_wstrb' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_wlast' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_wvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_bready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_araddr' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arlen' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arsize' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arburst' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arlock' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arcache' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arprot' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_aruser' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_rready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_awqos' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp0_arqos' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp1_awuser' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp1_aruser' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp2_awuser' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'maxigp2_aruser' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_awready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_wready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_bid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_bresp' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_bvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_arready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_rid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_rdata' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_rresp' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_rlast' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp0_rvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_awready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_wready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_bid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_bresp' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_bvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_arready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_rid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_rdata' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_rresp' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_rlast' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp1_rvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_awready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_wready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_bid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_bresp' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_bvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_arready' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_rid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_rdata' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_rresp' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_rlast' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp5_rvalid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp6_bid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'saxigp6_rid' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'emio_gpio_t' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'pl_resetn1' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'pl_resetn2' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'pl_resetn3' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7071] port 'pl_clk1' of module 'kv260_bist_PS_0_0' is unconnected for instance 'PS_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
WARNING: [Synth 8-7023] instance 'PS_0' of module 'kv260_bist_PS_0_0' has 412 connections declared, but only 340 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2302]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_gpio_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_gpio_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_gpio_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_gpio_0_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_gpio_1_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_gpio_1_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_gpio_1_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_gpio_1_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_iic_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_iic_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_iic_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_iic_0_0_stub.v:6]
WARNING: [Synth 8-7071] port 'gpo' of module 'kv260_bist_axi_iic_0_0' is unconnected for instance 'axi_iic_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2687]
WARNING: [Synth 8-7023] instance 'axi_iic_0' of module 'kv260_bist_axi_iic_0_0' has 27 connections declared, but only 26 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:2687]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_cap_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:4032]
INFO: [Synth 8-6157] synthesizing module 'm00_couplers_imp_14OINKA' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:9308]
INFO: [Synth 8-6155] done synthesizing module 'm00_couplers_imp_14OINKA' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:9308]
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_1UTR28B' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:12139]
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_1UTR28B' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:12139]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_cap_imp_s00_mmu_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_s00_mmu_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_cap_imp_s00_mmu_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_s00_mmu_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 's01_couplers_imp_15JT4CT' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:13482]
INFO: [Synth 8-6155] done synthesizing module 's01_couplers_imp_15JT4CT' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:13482]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_cap_imp_s01_mmu_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_s01_mmu_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_cap_imp_s01_mmu_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_s01_mmu_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 's02_couplers_imp_G48EIV' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:14015]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_cap_imp_auto_us_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_auto_us_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_cap_imp_auto_us_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_auto_us_0_stub.v:6]
WARNING: [Synth 8-7071] port 'm_axi_awregion' of module 'kv260_bist_axi_interconnect_cap_imp_auto_us_0' is unconnected for instance 'auto_us' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:14226]
WARNING: [Synth 8-7071] port 'm_axi_arregion' of module 'kv260_bist_axi_interconnect_cap_imp_auto_us_0' is unconnected for instance 'auto_us' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:14226]
WARNING: [Synth 8-7023] instance 'auto_us' of module 'kv260_bist_axi_interconnect_cap_imp_auto_us_0' has 72 connections declared, but only 70 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:14226]
INFO: [Synth 8-6155] done synthesizing module 's02_couplers_imp_G48EIV' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:14015]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_cap_imp_s02_mmu_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_s02_mmu_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_cap_imp_s02_mmu_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_s02_mmu_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_cap_imp_xbar_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_xbar_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_cap_imp_xbar_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_cap_imp_xbar_0_stub.v:6]
WARNING: [Synth 8-7071] port 's_axi_bid' of module 'kv260_bist_axi_interconnect_cap_imp_xbar_0' is unconnected for instance 'xbar' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:5199]
WARNING: [Synth 8-7071] port 's_axi_rid' of module 'kv260_bist_axi_interconnect_cap_imp_xbar_0' is unconnected for instance 'xbar' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:5199]
WARNING: [Synth 8-7071] port 'm_axi_awregion' of module 'kv260_bist_axi_interconnect_cap_imp_xbar_0' is unconnected for instance 'xbar' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:5199]
WARNING: [Synth 8-7071] port 'm_axi_arregion' of module 'kv260_bist_axi_interconnect_cap_imp_xbar_0' is unconnected for instance 'xbar' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:5199]
WARNING: [Synth 8-7023] instance 'xbar' of module 'kv260_bist_axi_interconnect_cap_imp_xbar_0' has 78 connections declared, but only 74 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:5199]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_cap_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:4032]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_ctrl_100_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:5276]
INFO: [Synth 8-6157] synthesizing module 'm00_couplers_imp_MBSZ6A' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:9980]
INFO: [Synth 8-6155] done synthesizing module 'm00_couplers_imp_MBSZ6A' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:9980]
INFO: [Synth 8-6157] synthesizing module 'm01_couplers_imp_EQMWD0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10210]
INFO: [Synth 8-6155] done synthesizing module 'm01_couplers_imp_EQMWD0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10210]
INFO: [Synth 8-6157] synthesizing module 'm02_couplers_imp_16XE9WE' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10452]
INFO: [Synth 8-6155] done synthesizing module 'm02_couplers_imp_16XE9WE' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10452]
INFO: [Synth 8-6157] synthesizing module 'm03_couplers_imp_1YZBBH4' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10694]
INFO: [Synth 8-6155] done synthesizing module 'm03_couplers_imp_1YZBBH4' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10694]
INFO: [Synth 8-6157] synthesizing module 'm04_couplers_imp_8HHJRF' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10924]
INFO: [Synth 8-6155] done synthesizing module 'm04_couplers_imp_8HHJRF' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10924]
INFO: [Synth 8-6157] synthesizing module 'm05_couplers_imp_YE2MFH' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:11154]
INFO: [Synth 8-6155] done synthesizing module 'm05_couplers_imp_YE2MFH' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:11154]
INFO: [Synth 8-6157] synthesizing module 'm06_couplers_imp_1MX6287' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:11396]
INFO: [Synth 8-6155] done synthesizing module 'm06_couplers_imp_1MX6287' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:11396]
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_DXU6S3' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:12594]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_ctrl_100_imp_auto_pc_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_DXU6S3' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:12594]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0_stub.v:6]
WARNING: [Synth 8-689] width (6) of port connection 'm_axi_arprot' does not match port width (21) of module 'kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:6275]
WARNING: [Synth 8-689] width (6) of port connection 'm_axi_awprot' does not match port width (21) of module 'kv260_bist_axi_interconnect_ctrl_100_imp_xbar_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:6279]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_ctrl_100_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:5276]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_ctrl_300_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:6314]
INFO: [Synth 8-6157] synthesizing module 'm00_couplers_imp_J77J3X' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:9543]
INFO: [Synth 8-6155] done synthesizing module 'm00_couplers_imp_J77J3X' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:9543]
INFO: [Synth 8-6157] synthesizing module 'm01_couplers_imp_8YZKFV' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10095]
INFO: [Synth 8-6155] done synthesizing module 'm01_couplers_imp_8YZKFV' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10095]
INFO: [Synth 8-6157] synthesizing module 'm02_couplers_imp_13Y8R8X' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10337]
INFO: [Synth 8-6155] done synthesizing module 'm02_couplers_imp_13Y8R8X' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10337]
INFO: [Synth 8-6157] synthesizing module 'm03_couplers_imp_1T3FLPZ' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10567]
INFO: [Synth 8-6155] done synthesizing module 'm03_couplers_imp_1T3FLPZ' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10567]
INFO: [Synth 8-6157] synthesizing module 'm04_couplers_imp_3AKSO4' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10809]
INFO: [Synth 8-6155] done synthesizing module 'm04_couplers_imp_3AKSO4' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:10809]
INFO: [Synth 8-6157] synthesizing module 'm05_couplers_imp_UPY542' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:11039]
INFO: [Synth 8-6155] done synthesizing module 'm05_couplers_imp_UPY542' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:11039]
INFO: [Synth 8-6157] synthesizing module 'm06_couplers_imp_1HKI560' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:11269]
INFO: [Synth 8-6155] done synthesizing module 'm06_couplers_imp_1HKI560' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:11269]
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_AY8IIK' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:12350]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_ctrl_300_imp_auto_pc_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_AY8IIK' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:12350]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axi_interconnect_ctrl_300_imp_xbar_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_ctrl_300_imp_xbar_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_ctrl_300_imp_xbar_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axi_interconnect_ctrl_300_imp_xbar_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axi_interconnect_ctrl_300_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:6314]
INFO: [Synth 8-6157] synthesizing module 'capture_pipeline_ias_imp_7N7NFP' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:13]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axis_data_fifo_cap_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_data_fifo_cap_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axis_data_fifo_cap_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_data_fifo_cap_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axis_subset_converter_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_subset_converter_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axis_subset_converter_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_subset_converter_0_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_mipi_csi2_rx_subsyst_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_mipi_csi2_rx_subsyst_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_mipi_csi2_rx_subsyst_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_mipi_csi2_rx_subsyst_0_0_stub.v:6]
WARNING: [Synth 8-7071] port 'rxbyteclkhs' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_0' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:441]
WARNING: [Synth 8-7071] port 'system_rst_out' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_0' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:441]
WARNING: [Synth 8-7071] port 'frame_rcvd_pulse_out' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_0' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:441]
WARNING: [Synth 8-7023] instance 'mipi_csi2_rx_subsyst_0' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_0' has 38 connections declared, but only 35 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:441]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_v_demosaic_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_demosaic_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_v_demosaic_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_demosaic_0_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_v_frmbuf_wr_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_frmbuf_wr_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_v_frmbuf_wr_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_frmbuf_wr_0_0_stub.v:6]
WARNING: [Synth 8-7071] port 'm_axi_mm_video_AWREGION' of module 'kv260_bist_v_frmbuf_wr_0_0' is unconnected for instance 'v_frmbuf_wr_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:516]
WARNING: [Synth 8-7071] port 'm_axi_mm_video_ARREGION' of module 'kv260_bist_v_frmbuf_wr_0_0' is unconnected for instance 'v_frmbuf_wr_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:516]
WARNING: [Synth 8-7023] instance 'v_frmbuf_wr_0' of module 'kv260_bist_v_frmbuf_wr_0_0' has 64 connections declared, but only 62 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:516]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_v_proc_ss_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_proc_ss_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_v_proc_ss_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_proc_ss_0_0_stub.v:6]
WARNING: [Synth 8-7071] port 'aresetn_io_axis' of module 'kv260_bist_v_proc_ss_0_0' is unconnected for instance 'v_proc_ss_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:579]
WARNING: [Synth 8-7023] instance 'v_proc_ss_0' of module 'kv260_bist_v_proc_ss_0_0' has 41 connections declared, but only 40 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:579]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_xlslice_1_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_1_0/synth/kv260_bist_xlslice_1_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_xlslice_1_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_1_0/synth/kv260_bist_xlslice_1_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_xlslice_2_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_2_0/synth/kv260_bist_xlslice_2_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_xlslice_2_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_2_0/synth/kv260_bist_xlslice_2_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_xlslice_3_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_3_0/synth/kv260_bist_xlslice_3_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized1' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized1' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_xlslice_3_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_3_0/synth/kv260_bist_xlslice_3_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'capture_pipeline_ias_imp_7N7NFP' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:13]
INFO: [Synth 8-6157] synthesizing module 'capture_pipeline_isp_imp_R9VKSN' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:631]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axis_data_fifo_cap_1' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_data_fifo_cap_1_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axis_data_fifo_cap_1' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_data_fifo_cap_1_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axis_subset_converter_0_1' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_subset_converter_0_1_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axis_subset_converter_0_1' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_subset_converter_0_1_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_mipi_csi2_rx_subsyst_0_1' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_mipi_csi2_rx_subsyst_0_1_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_mipi_csi2_rx_subsyst_0_1' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_mipi_csi2_rx_subsyst_0_1_stub.v:6]
WARNING: [Synth 8-7071] port 'rxbyteclkhs' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_1' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:922]
WARNING: [Synth 8-7071] port 'clkoutphy_out' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_1' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:922]
WARNING: [Synth 8-7071] port 'pll_lock_out' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_1' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:922]
WARNING: [Synth 8-7071] port 'system_rst_out' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_1' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:922]
WARNING: [Synth 8-7071] port 'frame_rcvd_pulse_out' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_1' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:922]
WARNING: [Synth 8-7023] instance 'mipi_csi2_rx_subsyst_0' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_1' has 38 connections declared, but only 33 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:922]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_v_frmbuf_wr_0_1' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_frmbuf_wr_0_1_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_v_frmbuf_wr_0_1' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_frmbuf_wr_0_1_stub.v:6]
WARNING: [Synth 8-7071] port 'm_axi_mm_video_AWREGION' of module 'kv260_bist_v_frmbuf_wr_0_1' is unconnected for instance 'v_frmbuf_wr_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:956]
WARNING: [Synth 8-7071] port 'm_axi_mm_video_ARREGION' of module 'kv260_bist_v_frmbuf_wr_0_1' is unconnected for instance 'v_frmbuf_wr_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:956]
WARNING: [Synth 8-7023] instance 'v_frmbuf_wr_0' of module 'kv260_bist_v_frmbuf_wr_0_1' has 64 connections declared, but only 62 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:956]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_xlslice_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_0_0/synth/kv260_bist_xlslice_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized2' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized2' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_xlslice_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_0_0/synth/kv260_bist_xlslice_0_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'capture_pipeline_isp_imp_R9VKSN' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:631]
INFO: [Synth 8-6157] synthesizing module 'capture_pipeline_raspi_imp_1FC7JYS' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1024]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axis_data_fifo_cap_2' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_data_fifo_cap_2_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axis_data_fifo_cap_2' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_data_fifo_cap_2_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_axis_subset_converter_0_2' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_subset_converter_0_2_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_axis_subset_converter_0_2' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_axis_subset_converter_0_2_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_mipi_csi2_rx_subsyst_0_2' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_mipi_csi2_rx_subsyst_0_2_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_mipi_csi2_rx_subsyst_0_2' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_mipi_csi2_rx_subsyst_0_2_stub.v:6]
WARNING: [Synth 8-7071] port 'rxbyteclkhs' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_2' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1452]
WARNING: [Synth 8-7071] port 'frame_rcvd_pulse_out' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_2' is unconnected for instance 'mipi_csi2_rx_subsyst_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1452]
WARNING: [Synth 8-7023] instance 'mipi_csi2_rx_subsyst_0' of module 'kv260_bist_mipi_csi2_rx_subsyst_0_2' has 37 connections declared, but only 35 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1452]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_v_demosaic_0_1' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_demosaic_0_1_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_v_demosaic_0_1' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_demosaic_0_1_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_v_frmbuf_wr_0_2' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_frmbuf_wr_0_2_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_v_frmbuf_wr_0_2' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_frmbuf_wr_0_2_stub.v:6]
WARNING: [Synth 8-7071] port 'm_axi_mm_video_AWREGION' of module 'kv260_bist_v_frmbuf_wr_0_2' is unconnected for instance 'v_frmbuf_wr_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1527]
WARNING: [Synth 8-7071] port 'm_axi_mm_video_ARREGION' of module 'kv260_bist_v_frmbuf_wr_0_2' is unconnected for instance 'v_frmbuf_wr_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1527]
WARNING: [Synth 8-7023] instance 'v_frmbuf_wr_0' of module 'kv260_bist_v_frmbuf_wr_0_2' has 64 connections declared, but only 62 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1527]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_v_proc_ss_0_1' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_proc_ss_0_1_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_v_proc_ss_0_1' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_v_proc_ss_0_1_stub.v:6]
WARNING: [Synth 8-7071] port 'aresetn_io_axis' of module 'kv260_bist_v_proc_ss_0_1' is unconnected for instance 'v_proc_ss_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1590]
WARNING: [Synth 8-7023] instance 'v_proc_ss_0' of module 'kv260_bist_v_proc_ss_0_1' has 41 connections declared, but only 40 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1590]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_xlslice_4_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_4_0/synth/kv260_bist_xlslice_4_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized3' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized3' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_xlslice_4_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_4_0/synth/kv260_bist_xlslice_4_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_xlslice_5_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_5_0/synth/kv260_bist_xlslice_5_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized4' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized4' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_xlslice_5_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_5_0/synth/kv260_bist_xlslice_5_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_xlslice_6_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_6_0/synth/kv260_bist_xlslice_6_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized5' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized5' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_xlslice_6_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/ip/kv260_bist_xlslice_6_0/synth/kv260_bist_xlslice_6_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'capture_pipeline_raspi_imp_1FC7JYS' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:1024]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_clk_wiz_0_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_clk_wiz_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_clk_wiz_0_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_clk_wiz_0_0_stub.v:6]
WARNING: [Synth 8-7071] port 'locked' of module 'kv260_bist_clk_wiz_0_0' is unconnected for instance 'clk_wiz_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:3535]
WARNING: [Synth 8-7023] instance 'clk_wiz_0' of module 'kv260_bist_clk_wiz_0_0' has 7 connections declared, but only 6 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.gen/sources_1/bd/kv260_bist/synth/kv260_bist.v:3535]
INFO: [Synth 8-6157] synthesizing module 'kv260_bist_proc_sys_reset_100MHz_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_proc_sys_reset_100MHz_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kv260_bist_proc_sys_reset_100MHz_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kv260/platforms/kv260_bist/project/kv260_bist.runs/synth_1/.Xil/Vivado-110657-logictronix05-MS-7E26/realtime/kv260_bist_proc_sys_reset_100MHz_0_stub.v:6]
...
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