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● VIVADO/Vitis 2022.2
● Petalinux 2022.2
● Platform used- Xilinx KR260 Evaluation Board
Design Flow:VIVADO/Vitis Tool Flow:● Insert a Zynq UltraScale+ MPSoC IP block and run block automation and apply the block preset.
● Disable the two full power ports and enable the low power high performance port.
● Change the I/O configuration for the Zynq UltraScale+ MPSoC IP block under Low Speed I/O peripherals.
● Enable I2C 1 on MIO 24- 25, SPI 1 on MIO 6-11, UART 1 on MIO 36-37 and enable GPIO0 MIO and GPIO1 MIO.
● Under Processing Unit > TTC, enable Waveout for TTC 0 with EMIO as I/O.
● Under High Speed, enable GEM 0 on GT Lane0 and GEM 1 on MIO pins 38 - 49 with its MDIO 1 on MIO pins 50 -51.
● For USB0, enable USB 0 on MIO pins 52 - 63 and USB 3.0 on GT Lane2.
● For USB1, enable USB 1 on MIO pins 64 - 75 and USB 3.0 on GT Lane3.
● Select a separate MIO pin with an active low polarity for USB reset and put the reset for USB 0 and USB 1 reset on MIO pin 76 and 77 respectively.
● Enable the DisplayPort on MIO pins 27 - 30 with a Single Lower lane selection on GT Lane1.
● Under PS-PL Configuration > General > Fabric Reset Enable, increase Number of Fabric Resets to 4.
● Verify the peripherals in the design.
● Add the Clocking Wizard and change the reset type to active low under the Output Clocks tab.
● Enable two clock outputs (100 MHz and 25 MHz) on the Clocking Wizard.
● Connect the clock and reset of the Clocking Wizard and the Zynq UltraScale+ MPSoC IPs.
● Add Processing System Reset IP and connect its reset to the PL reset and sync clock to the clock output of the Clocking Wizard.
● Add the AXI Interrupt Controller and change the interrupt output connection to single under the Basic tab.
● While running the connection automation for the block, select the output of Clocking Wizard to be the clock source.
● Connect the interrupt output of the interrupt controller to the interrupt input of the PS.
Enabling Interfaces in the Platform Setup Window
● Enable all except the low performance AXI ports from the Zynq UltraScale+ MPSoc IP.
● Also assign SP Tag as shown below.
● Enable 8 general purpose master AXI interfaces from the AXI interconnect.
● Enable the clocks from the Clocking Wizard and set the 100MHz clock as default.
● Enable the interrupt from the Interrupt Controller.
● Disable incremental synthesis under project settings.
● Enable the -bin_file options under Bitstream settings.
● Modify the Clocking Wizard to enable a second clock of 25 MHz and enable it in the Platform Setup. If you previously enabled it, skip this step.
● Add a new Processor Reset System block and connect its ext_reset_in to the PL reset and sync clock to the 25 MHz clock output of the Clocking Wizard.
● Add IIC IP with default settings.
● Connect its reset to peripheral_aresetn of the second processor system reset and clock to clk_out2 which is the 25 MHz clock and run the connection automation.
● Connect the iic2intc_irpt output of the IIC block to the intr input of the AXI Interrupt Controller.
Note: We will be using using AXI IIC for I2C communication with sensor on "Next Tutorial". In this tutorial, we will have demo on GPIO mainly.
● Add a GPIO block and set its GPIO Width to 8.
● Run connection automation for the GPIO block.
● Rename the external ports if you like.
● Validate the design.
● Add the following constraints.
######################## PMOD 1 Upper ########################
set_property PACKAGE_PIN H12 [get_ports {pmod1_tri_io[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod1_tri_io[0]}]
set_property PACKAGE_PIN E10 [get_ports {pmod1_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod1_tri_io[1]}]
set_property PACKAGE_PIN D10 [get_ports {pmod1_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod1_tri_io[2]}]
set_property PACKAGE_PIN C11 [get_ports {pmod1_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod1_tri_io[3]}]
######################## PMOD 1 Lower ########################
set_property PACKAGE_PIN B10 [get_ports {pmod1_tri_io[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod1_tri_io[4]}]
set_property PACKAGE_PIN E12 [get_ports {pmod1_tri_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod1_tri_io[5]}]
set_property PACKAGE_PIN D11 [get_ports {pmod1_tri_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod1_tri_io[6]}]
set_property PACKAGE_PIN B11 [get_ports {pmod1_tri_io[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod1_tri_io[7]}]
#RPi IIC
set_property PACKAGE_PIN AE15 [get_ports {iic_sda_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {iic_sda_io}]
set_property PACKAGE_PIN AE14 [get_ports {iic_scl_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {iic_scl_io}]● Generate the wrapper for the block design, synthesize and generate the bitstream for the design.
● After the generation, export the design.
Building Petalinux with the Exported PlatformPrerequisites:● Download the supported BSP for the board from Xilinx downloads.
● Download link:
Create a petalinux project● Create a folder and copy the platform (XSA) exported from Vivado.
● Also copy the BIN file generated by Vivado located in <VIVADO_PROJECT_DIR>/<DESIGN_NAME>.runs/impl_1/<DESIGN_WRAPPER_NAME>.bin
● Open a terminal in the directory and source the petalinux script.
● Run the command below to create a petalinux project named <project-name>.
○ petalinux-create --type project -s <location-to-bsp> --name <project-name>
● Run the command below to configure the project.
○ petalinux-config --get-hw-description <path-to-xsa/xsa-dir>
● In the project configuration window,
○ Enable FPGA Manager under FPGA Manager.
- Under Image Packaging Configuration,
■ Change Root filesystem type to INITRD
■ Change INITRAMFS/INITRD Image name to petalinux-initramfs-image
■ Disable Copy final images to tftpboot
- Save and exit the configuration window.
● Run the following to configure the kernel.
○ petalinux-config -c kernel
○ Under Device Drivers > I2C support > I2C Hardware Bus support, enable
- Cadence I2C Controller
- Xilinx I2C Controller
- Save and exit the configuration.
● Run the following to configure the root filesystem.
petalinux-config -c rootfs○ Under Filesystem Packages > base > i2c-tools, enable
- i2c-tools
- i2c-tools-dev
● Run petalinux-build to build the project.
● Run the following command to create a bootable WIC image.
petalinux-package --wic --images-dir images/linux/ --bootfiles "ramdisk.cpio.gz.u-boot, boot.scr, Image, system.dtb, system-zynqmp-sck-kr-g-revB.dtb" --disk-name "sda"○ Make sure the dtb file is present in the images/linux/ directory.
● Run BalenEtcher.
● Locate the WIC image in images/linux directory.
● Select the target device and select Flash.
● Open a terminal, in the directory where the XSA was copied. Source Petalinux again here and run the xsct command.
● If the system cannot find the xsct command, make sure to source the Vitis or PetaLinux shell script.
● If the xsct command is still missing after running the Petalinux shell script, run the following command.
○ PATH="${XSCT_TOOLCHAIN}/bin:${PATH}"
● Running the following “HSI” command will extract the contents of the xsa in the current directory.
hsi::open_hw_design ./<xsa-name>.xsa● Now run,
createdts -hw ./<xsa-name>.xsa -zocl -platform-name <any-platform-name> -git-branch <git-branch> -overlay -compile -out ./<any-non-existing-dir-name-is-better>○ Running the above command will:
■ Clone the branch <git-branch> from the Xilinx device tree generator repo
■ Generate the device tree (pl.dtsi) in./<any-non-existing-dir-name-is-better>/<any-non-existing-dir-name-is-better>/<any-platform-name>/psu_cortexa53_0/device_tree_domain/bsp/ directory
● Exit the xsct shell.
Note: The following command can be run in a regular terminal without Petalinux script sourced.
● Run the following command to compile the device tree.
dtc -@ -O dtb -o ./kr260.dtbo ./kr260_dt/kr260_dt/kr260/psu_cortexa53_0/device_tree_domain/bsp/pl.dtsi- Make sure to edit the path to the pl.dtsi.
○ This command with generate kr260.dtbo in the current directory.
○ If dtc throws “dtc: invalid option -- '@'” error, you will need to compile dtc yourself.
Compiling DTC● Run the following commands.
git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git
cd dtc
make■ If you encounter ‘cc1: all warnings being treated as errors’, edit the Makefile in the dtc directory and remove the -Werror flag from CFLAGS.
make install■ Running the above command will install dtc in $HOME/bin.
Retrying to Compile the Device Tree● Run cd../ to move out of the dtc directory
● Now run,
dtc -@ -O dtb -o ./kr260.dtbo ./kr260_dt/kr260_dt/kr260/psu_cortexa53_0/device_tree_domain/bsp/pl.dtsi● Run the following command to create shell.json.
echo '{ "shell_type" : "XRT_FLAT", "num_slots": "1" }' > shell.json● Rename the bin file from the Vivado implementation directory the same as you named the dtbo.
○ I have renamed them to kr260.bit.bin and kr260.dtbo.
● Boot the device now and login.
○ The username and password is petalinux by default.
● Create a directory in the device home directory.
mkdir ~/<any-directory-name>● Connect your device to your router and find the ip address by running the ifconfig command. Better if you assign a static IP for the device in your router settings.
● Run the scp command on the host machine to transfer the files to the device.
scp ./kr260.bit.bin ./kr260.dtbo ./shell.json petalinux@<DEVICE_IP>:~/<directory-you-created-earlier>● Move the directory that contains the kr260.bit.bin, kr260.dtbo and shell.json to /lib/firmware/xilinx/.
sudo mv ./<directory-you-created-earlier> /lib/firmware/xilinx/● List the apps present on the device.
sudo xmutil listapps● Unload the current app.
sudo xmutil unloadapp● Load your app (kr260 in this case).
sudo xmutil loadapp kr260● Run
cd into /sys/class/gpio/ and run ls- This will list out the GPIOs available in the system.
● Print out the label of the gppiochip to see what it relates to.
○ cat ./<gpiochip>/label● The output should relate to AXI GPIO’s address from the Vivado block design address editor.
○ For example, gpiochip492’s label 80010000 is the address assigned to the GPIO block in this design.
● Export and set the direction of the first pin.
echo 492 | sudo tee ./export
echo out | sudo tee ./gpio492/direction○ Do the same if required for the other pins, increment the number by 1 for each next pin.
GPIO-Control: Writing to the pin○ Run, following command to set the pin HIGH
echo 1 | sudo tee ./gpio492/value○Run following command to set the pin LOW
echo 0 | sudo tee ./gpio492/valueThanks to our team member, Frank Shrestha for creating this Tutorial!
![LogicTronix [FPGA Design + Machine Learning Company]](https://hackster.imgix.net/uploads/attachments/1123066/_SyVIfEqFUU.blob?auto=compress%2Cformat&w=60&h=60&fit=min&dpr=2)
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