LogicTronix [FPGA Design + Machine Learning Company]

Published July 14, 2025 © GPL3+

KD240 BIST - Platform/App Recreating with 2025.1 Vitis & HLS

Re-creating the KD240 BIST application with 2025.1.

IntermediateFull instructions provided3 hours149

KD240 BIST - Platform/App Recreating with 2025.1 Vitis & HLS

Things used in this project

Hardware components

AMD Kria™ KD240 Drives Starter Kit

Software apps and online services

AMD Vitis Unified Software Platform

Story

In this tutorial, we will be re-creating the KD240 BIST hardware platform in 2025.1 VIVADO/Vitis/HLS tools. KD240 BIST consists of PL Ethernet design, AXI CAN , ADC and PS interface based design , so it is quite important resource for those who are working with those interfaces on KD240 or other Kria or MPSoC boards.

A. Overview

Kria KD240 Drives Kit based BIST source is updated till 2024.1, while there is BIST firmware available for 2024.2. But there is no source update mentioned for this or newer version.

We want to re-create the BIST application in 2025.1 for KD240. This BIST design is important design reference for K24 custom carrier and KD240, so we are creating this tutorial.

B. Steps performed:

1. Git clone the repo – recursive approach or add vitis libraries later.

Option A [preferred]:

git clone --recursive https://github.com/Xilinx/kria-vitis-platforms.git

Option B:

Download source code ZIP from here: https://github.com/Xilinx/kria-vitis-platforms/releases/tag/v1.0.1

Extract it, and then clone :

git clone --recursive https://github.com/Xilinx/kria-vitis-platforms.git

Now copy the Vitis Librariesfolder (sources) from here to v1.0.1

2. Now, goto KD240 directory

cd ./kd240/platforms/kd240_bist

3. Run the make command, this make commands runs separate HLS scripts which were initially based in older version. Since 2025.1 tool version, the run method or command for HLS script has changed. So you might got error similar to this one:

$ make xsa
make[1]: vitis_hls: No such file or directory
make[1]: vitis_hls: No such file or directory
make[1]: *** [Makefile:24: ip] Error 127
make: *** [Makefile:45: ../ip/qei/*.prj/sol1/impl/export.zip] Error 2
ambiguous command name "make": make_bd_intf_pins_external make_bd_pins_external make_diff_pair_ports make_wrapper

4. Now to resolve above mentioned error, modify the HLS IP make script:

Inside kd240/platforms/ip/qei/, open Makefile, modify at line no 5 and 24:

HLS = vitis-run

$(HLS) --mode hls --tcl run_hls.tcl

5. Modify similarly for other IP also, foc, svpwm_duty and pwm_gen

6. Now run the make command:

kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist$ make xsa

7. You can see the terminal log, according to CPU/RAM availability on PC the design can get generated by around 30min.

8. Now you can lunch VIVADO and check the block design, resource usage and other info:

9. KD240 BIST has been generated, now using XSA one can create the DTSI (follow device tree generation tutorial) and then create DTBO by compiling the DTSI. The BIT inside XSA can be renamed as BIN and JSON file can be copy from Kria-App-firmware github repo [Link].

10. Now we are ready for copy and load firmware by now. One can copy and load the firmware into KD240 (Petalinux or Ubuntu) and run the same KD240 python applications from KD240 BIST page - Link.

11. By following this BIST application one can also create own custom hardware or IP block design and integrated in Kria BIST app flow. For example, adding logic (on top of acquired data from BIST interfaces) which is not there at BIST platform design.

12. XSA, BIT file can also be found at github repo or at attachment of this article/tutorial.

13. Build log and VIVADO block design PDF is also attached below section.

14. At next section , we will copy these BIST firmware files to KD240 and run there with BIST App and custom app.

C. Preparing Setup and Running BIST on KD240

a. Running BIST firmware in Kria-Petalinux

i. One has to either use the WIC image of Petalinux

Download and burn AMD Download, this is generic WIC image supported for all three Kria starter kits.

ii. Or, has to create the WIC image using the provided BSP in Petalinux 2025.1 version:

Download 2025.1 SDT flow BSP for KD240 starter kit - AMD download
Build process could be as like as 2023.2 version commands as mentioned here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+SOMs+Starter+Kits#PetaLinux-Build-instructions. From this step generate the WIC image , burn it on SD card using Balena Etcher and boot the SD on KD240. Here also update the boot firmware , one can select the newest firmware and update in KD240.
After booting, for the BIST application, when Python support is enabled in Petalinux project, one can run the "sudo apt install" for BIST python packages from here: https://github.com/Xilinx/kria-bist
After libraries and support installed, one can follow the Kria-BIST app run flow from here: https://xilinx.github.io/kria-apps-docs/kd240/build/html/docs/bist/docs/run.html

b. Running BIST firmware in Kria-Ubuntu

For Ubuntu 22.04LTS you can just copy the firmwares and place into /lib/firmware/Xilinx/kd240-bist and then load with KD240 BIST docker image approach.

15. Similarly one can re-generate or design motor control and other custom drive application based platform including application from : https://github.com/Xilinx/kria-vitis-platforms/tree/main/kd240/platforms

The Git repo of this recreating KD240-BIST in 2025.1 is at here: https://github.com/LogicTronixInc/Recreating-Kria-BIST-2025.1

Thanks for going through this BIST recreation tutorial!

For any queries around it or custom carrier based BIST application development, please contact us at info@LogicTronix.com.

LogicTronix is AMD-Xilinx Partner for FPGA Design and ML Acceleration!

Code

KD240-BIST-20251-build-log

# We already make the ip/qui and ip/foc vitis hls project manually, manual mae not needed now.
# If you are following Makefile modificatin step then you dont need to do any manual step.
# Below section resume from next vitis hls IP - svpwn_duty and then pwm_gen.


logictronix05@logictronix05-MS-7E26:/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist$ make xsa
make -C ../ip/svpwm_duty ip 
make[1]: Entering directory '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty'
vitis-run --mode hls --tcl run_hls.tcl

****** vitis-run v2025.1 (64-bit)
  **** SW Build 6137779 on 2025-05-21-18:10:03
  **** Start of session at: Sun Jul 13 14:57:19 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

  **** HLS Build v2025.1 6135595
Sourcing Tcl script '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset ip_svpwm_duty.prj 
WARNING: [HLS 200-2182] The 'ip_svpwm_duty.prj' project will not automatically appear within Vitis IDE workspaces and is meant only for TCL batch use.  Please use open_component instead of open_project/open_solution to generate Vitis IDE compatible component files and directory structure.
Resolution: For help on HLS 200-2182 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2025.1%20English&url=ug1448-hls-guidance&resourceid=200-2182.html
INFO: [HLS 200-10] Creating and opening solution '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj'.
INFO: [HLS 200-1510] Running: add_files ../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/ip_svpwm.cpp -cflags -I../../../../common/Vitis_Libraries/motor_control/L1/include/hw -I../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src 
INFO: [HLS 200-10] Adding design file '../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/ip_svpwm.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb ../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/test_svpwm.cpp -cflags -I../../../../common/Vitis_Libraries/motor_control/L1/include/hw -I../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src 
INFO: [HLS 200-10] Adding test bench file '../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/test_svpwm.cpp' to the project
INFO: [HLS 200-1510] Running: set_top hls_svpwm_duty 
INFO: [HLS 200-1510] Running: open_solution -reset sol1 
INFO: [HLS 200-10] Creating and opening solution '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1'.
INFO: [HLS 200-10] Cleaning up the solution database.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2025.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html
INFO: [HLS 200-1510] Running: set_part xck24-ubva530-2LV-c 
INFO: [HLS 200-1611] Setting target device to 'xck24-ubva530-2LV-c'
INFO: [HLS 200-1510] Running: create_clock -period 10 
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1510] Running: set_clock_uncertainty 1.25 
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.25ns.
INFO: [HLS 200-1510] Running: csynth_design 
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.2 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.24 seconds; current allocated memory: 387.410 MB.
INFO: [HLS 200-10] Analyzing design file '../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/ip_svpwm.cpp' ... 
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 2.14 seconds. CPU system time: 0.41 seconds. Elapsed time: 2.55 seconds; current allocated memory: 390.555 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-1995] There were 5,740 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 830 instructions in the design after the 'Unroll/Inline (step 1)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 357 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 360 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 340 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 260 instructions in the design after the 'Array/Struct (step 1)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 260 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 262 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 318 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 322 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 322 instructions in the design after the 'Performance (step 1)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 322 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 321 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 321 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 323 instructions in the design after the 'HW Transforms (step 1)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 353 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 214-178] Inlining function 'ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0> xf::motorcontrol::details::GetVoff<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0> >(ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>*)' into 'void xf::motorcontrol::details::calculate_ratios_core<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0> >(ap_ufixed<17, 1, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, int, int)' (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:148:0)
INFO: [HLS 214-178] Inlining function 'void xf::motorcontrol::details::calculate_ratios_core<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0> >(ap_ufixed<17, 1, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>*, ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, int, int)' into 'void xf::motorcontrol::details::calculate_ratios<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >(hls::stream<xf::motorcontrol::details::pwmStrmIO<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0> >, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, int volatile&, int volatile&, int volatile&, int volatile&, int volatile&, int volatile&)' (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:178:0)
INFO: [HLS 214-241] Aggregating fifo (hls::stream) variable 'strm_pwm_io_bundle' with compact=bit mode in 97-bits (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:666:49)
INFO: [HLS 214-449] Automatically partitioning array 'duty_ratio' dimension 1 completely based on constant index. (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:182:22)
INFO: [HLS 214-270] Inferring pragma 'array_partition type=complete dim=1' for array 'duty_ratio' due to pipeline pragma (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:182:22)
INFO: [HLS 214-248] Applying array_partition to 'duty_ratio': Complete partitioning on dimension 1. (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:182:22)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 1.34 seconds. CPU system time: 0.37 seconds. Elapsed time: 6.36 seconds; current allocated memory: 400.574 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 400.574 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 400.805 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [XFORM 203-602] Inlining function 'xf::motorcontrol::details::GetRatio<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_ufixed<17, 1, (ap_q_mode)5, (ap_o_mode)3, 0> >' into 'xf::motorcontrol::details::calculate_ratios<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >' (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:163->../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:205) automatically.
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 401.484 MB.
INFO: [XFORM 203-602] Inlining function 'xf::motorcontrol::details::GetRatio<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_ufixed<17, 1, (ap_q_mode)5, (ap_o_mode)3, 0> >' into 'xf::motorcontrol::details::calculate_ratios<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >' (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:163->../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:205) automatically.
INFO: [XFORM 203-712] Applying dataflow to function 'xf::motorcontrol::hls_svpwm_duty_axi<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >' (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:669:1), detected/extracted 2 process function(s): 
	 'xf::motorcontrol::details::sampler_duty<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0> >'
	 'xf::motorcontrol::details::calculate_ratios<ap_fixed<24, 8, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >'.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.04 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 423.719 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 443.973 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'hls_svpwm_duty' ...
WARNING: [SYN 201-103] Legalizing function name 'sampler_duty<ap_fixed<24, 8, 5, 3, 0> >' to 'sampler_duty_ap_fixed_24_8_5_3_0_s'.
WARNING: [SYN 201-103] Legalizing function name 'calculate_ratios<ap_fixed<24, 8, 5, 3, 0>, ap_ufixed<16, 0, 5, 3, 0> >' to 'calculate_ratios_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_s'.
WARNING: [SYN 201-103] Legalizing function name 'hls_svpwm_duty_axi<ap_fixed<24, 8, 5, 3, 0>, ap_ufixed<16, 0, 5, 3, 0> >' to 'hls_svpwm_duty_axi_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_s'.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'sampler_duty_ap_fixed_24_8_5_3_0_s' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'LOOP_SVPWM_SAMPLER'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 1, loop 'LOOP_SVPWM_SAMPLER'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.03 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.04 seconds; current allocated memory: 444.309 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 444.309 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'calculate_ratios_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_s' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.03 seconds; current allocated memory: 444.309 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 444.309 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'hls_svpwm_duty_axi_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_s' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 444.309 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 444.309 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'hls_svpwm_duty' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 444.441 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 444.441 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'sampler_duty_ap_fixed_24_8_5_3_0_s' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'sampler_duty_ap_fixed_24_8_5_3_0_s'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 444.871 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'calculate_ratios_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_s' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Generating core module 'add_25s_25s_25_1_1': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'sdiv_40ns_24s_40_44_seq_1': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'calculate_ratios_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_s'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 447.480 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'hls_svpwm_duty_axi_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_s' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Finished creating RTL model for 'hls_svpwm_duty_axi_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_s'.
INFO: [RTMG 210-285] Implementing FIFO 'strm_pwm_io_bundle_U(hls_svpwm_duty_fifo_w97_d2_S)' using Shift Registers.
INFO: [RTMG 210-285] Implementing FIFO 'start_for_calculate_ratios_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_U0_U(hls_svpwm_duty_start_for_calculate_ratios_ap_fixed_24_8_5_3_0_ap_ufixed_16_0_5_3_0_U0)' using Shift Registers.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.03 seconds; current allocated memory: 450.117 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'hls_svpwm_duty' 
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/strm_Va_cmd' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/strm_Vb_cmd' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/strm_Vc_cmd' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/strm_dc_link' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/strm_duty_ratio_a' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/strm_duty_ratio_b' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/strm_duty_ratio_c' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/pwm_args_dc_link_ref' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/pwm_stt_cnt_iter' to 's_axilite & ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/pwm_args_dc_src_mode' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/pwm_args_sample_ii' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/pwm_stt_Va_cmd' to 's_axilite & ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/pwm_stt_Vb_cmd' to 's_axilite & ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_svpwm_duty/pwm_stt_Vc_cmd' to 's_axilite & ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on function 'hls_svpwm_duty' to 's_axilite & ap_ctrl_hs'.
WARNING: [RTGEN 206-101] Register 'pwm_args_cnt_trip_constprop' is power-on initialization.
INFO: [RTGEN 206-100] Bundling port 'pwm_args_dc_link_ref', 'pwm_stt_cnt_iter', 'pwm_args_dc_src_mode', 'pwm_args_sample_ii', 'pwm_stt_Va_cmd', 'pwm_stt_Vb_cmd', 'pwm_stt_Vc_cmd' and 'return' to AXI-Lite port pwm_args.
INFO: [RTGEN 206-100] Finished creating RTL model for 'hls_svpwm_duty'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 450.562 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.09 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.1 seconds; current allocated memory: 453.793 MB.
INFO: [HLS 200-111] Finished Updating report files: CPU user time: 0.24 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.29 seconds; current allocated memory: 458.523 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for hls_svpwm_duty.
INFO: [VLOG 209-307] Generating Verilog RTL for hls_svpwm_duty.
INFO: [HLS 200-789] **** Estimated Fmax: 118.01 MHz
INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 00:00:09; Allocated memory: 71.113 MB.
INFO: [HLS 200-1510] Running: config_export -ipname hls_svpwm_duty 
INFO: [HLS 200-1510] Running: export_design -rtl verilog -format ip_catalog 
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.

****** Vivado v2025.1 (64-bit)
  **** SW Build 6140274 on Wed May 21 22:58:25 MDT 2025
  **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025
  **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025
  **** Start of session at: Sun Jul 13 14:57:32 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
INFO: calling package_hls_ip ip_types=vitis sysgen json_file=/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/sol1_data.json outdir=/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/impl/ip srcdir=/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1 ippack_options_dict= ippack_options_dict=
INFO: Copied 1 ipmisc file(s) to /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/impl/ip/misc
INFO: Copied 18 verilog file(s) to /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/impl/ip/hdl/verilog
INFO: Copied 10 vhdl file(s) to /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/impl/ip/hdl/vhdl
INFO: Copied 10 swdriver file(s) to /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/impl/ip/drivers
INFO: Import ports from HDL: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/impl/ip/hdl/vhdl/hls_svpwm_duty.vhd (hls_svpwm_duty)
INFO: Add axi4lite interface s_axi_pwm_args
INFO: Add clock interface ap_clk
INFO: Add reset interface ap_rst_n
INFO: Add interrupt interface interrupt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.1/Vivado/data/ip'.
INFO: Add axi4stream interface strm_Va_cmd
INFO: Add axi4stream interface strm_Vb_cmd
INFO: Add axi4stream interface strm_Vc_cmd
INFO: Add axi4stream interface strm_dc_link
INFO: Add axi4stream interface strm_duty_ratio_a
INFO: Add axi4stream interface strm_duty_ratio_b
INFO: Add axi4stream interface strm_duty_ratio_c
INFO: Calling post_process_vitis to specialize IP
INFO: Calling post_process_sysgen to specialize IP
Generating sysgen info xml from json file
INFO: Created IP /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/impl/ip/component.xml
INFO: Created IP archive /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty/ip_svpwm_duty.prj/sol1/impl/ip/xilinx_com_hls_hls_svpwm_duty_1_0.zip
INFO: [Common 17-206] Exiting Vivado at Sun Jul 13 14:57:34 2025...
INFO: [HLS 200-802] Generated output file ip_svpwm_duty.prj/sol1/impl/export.zip
INFO: [HLS 200-2161] Finished Command export_design Elapsed time: 00:00:09; Allocated memory: 4.195 MB.
INFO: [HLS 200-112] Total CPU user time: 12.07 seconds. Total CPU system time: 2.1 seconds. Total elapsed time: 20.76 seconds; peak allocated memory: 462.719 MB.
INFO: [vitis-run 60-791] Total elapsed time: 0h 0m 21s
INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid.
make[1]: Leaving directory '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/svpwm_duty'
make -C ../ip/pwm_gen ip 
make[1]: Entering directory '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen'
vitis-run --mode hls --tcl run_hls.tcl

****** vitis-run v2025.1 (64-bit)
  **** SW Build 6137779 on 2025-05-21-18:10:03
  **** Start of session at: Sun Jul 13 14:57:41 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

  **** HLS Build v2025.1 6135595
Sourcing Tcl script '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset ip_pwm_gen.prj 
WARNING: [HLS 200-2182] The 'ip_pwm_gen.prj' project will not automatically appear within Vitis IDE workspaces and is meant only for TCL batch use.  Please use open_component instead of open_project/open_solution to generate Vitis IDE compatible component files and directory structure.
Resolution: For help on HLS 200-2182 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2025.1%20English&url=ug1448-hls-guidance&resourceid=200-2182.html
INFO: [HLS 200-10] Creating and opening solution '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj'.
INFO: [HLS 200-1510] Running: add_files ../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/ip_svpwm.cpp -cflags -I../../../../common/Vitis_Libraries/motor_control/L1/include/hw -I../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src 
INFO: [HLS 200-10] Adding design file '../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/ip_svpwm.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb ../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/test_svpwm.cpp -cflags -I../../../../common/Vitis_Libraries/motor_control/L1/include/hw -I../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src 
INFO: [HLS 200-10] Adding test bench file '../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/test_svpwm.cpp' to the project
INFO: [HLS 200-1510] Running: set_top hls_pwm_gen 
INFO: [HLS 200-1510] Running: open_solution -reset sol1 
INFO: [HLS 200-10] Creating and opening solution '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1'.
INFO: [HLS 200-10] Cleaning up the solution database.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2025.1%20English&url=ug1448-hls-guidance&resourceid=200-1505.html
INFO: [HLS 200-1510] Running: set_part xck24-ubva530-2LV-c 
INFO: [HLS 200-1611] Setting target device to 'xck24-ubva530-2LV-c'
INFO: [HLS 200-1510] Running: create_clock -period 10 
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1510] Running: set_clock_uncertainty 1.25 
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.25ns.
INFO: [HLS 200-1510] Running: csynth_design 
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.19 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.24 seconds; current allocated memory: 387.406 MB.
INFO: [HLS 200-10] Analyzing design file '../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/ip_svpwm.cpp' ... 
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 2.15 seconds. CPU system time: 0.42 seconds. Elapsed time: 2.57 seconds; current allocated memory: 390.496 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-1995] There were 7,387 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 677 instructions in the design after the 'Unroll/Inline (step 1)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 425 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 383 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 383 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 383 instructions in the design after the 'Array/Struct (step 1)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 383 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 383 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 383 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 367 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 367 instructions in the design after the 'Performance (step 1)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 367 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 367 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 367 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 391 instructions in the design after the 'HW Transforms (step 1)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 200-1995] There were 424 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details (/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/syn/report/csynth_design_size.rpt:2)
INFO: [HLS 214-131] Inlining function 'void xf::motorcontrol::details::generate_output_chnl<ap_uint<18> >(ap_uint<18>, ap_uint<18>, ap_uint<18>, ap_uint<18>, ap_uint<18>&, ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&)' into 'void xf::motorcontrol::details::PWM_gen_wave<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >(hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, int volatile&, int volatile&, int volatile&, long volatile&, int volatile&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, int volatile&, int volatile&, int volatile&, int volatile&)' (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:572:9)
INFO: [HLS 214-131] Inlining function 'bool CheckRange<int>(int&, RangeDef<int>&)' into 'void xf::motorcontrol::details::PWM_gen_wave<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >(hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, int volatile&, int volatile&, int volatile&, long volatile&, int volatile&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, int volatile&, int volatile&, int volatile&, int volatile&)' (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:513:5)
INFO: [HLS 214-178] Inlining function 'void xf::motorcontrol::hls_pwm_gen_axi<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >(hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, int volatile&, int volatile&, int volatile&, int volatile&, long volatile&, int volatile&, int volatile&, int volatile&, int volatile&)' into 'hls_pwm_gen(hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, hls::stream<ap_uint<1>, 0>&, int volatile&, int volatile&, int volatile&, int volatile&, int volatile&, int volatile&, int volatile&, int volatile&)' (../../../../common/Vitis_Libraries/motor_control/L1/tests/IP_SVPWM/src/ip_svpwm.cpp:103:0)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 1.31 seconds. CPU system time: 0.34 seconds. Elapsed time: 6.33 seconds; current allocated memory: 400.070 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 400.070 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 400.520 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.01 seconds; current allocated memory: 401.082 MB.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:556:9) to (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:575:13) in function 'xf::motorcontrol::details::PWM_gen_wave<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >'... converting 20 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:511:9) to (../../../../common/Vitis_Libraries/motor_control/L1/include/hw/svpwm.hpp:555:5) in function 'xf::motorcontrol::details::PWM_gen_wave<ap_ufixed<16, 0, (ap_q_mode)5, (ap_o_mode)3, 0> >'... converting 3 basic blocks.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 423.473 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 433.938 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'hls_pwm_gen' ...
WARNING: [SYN 201-103] Legalizing function name 'PWM_gen_wave<ap_ufixed<16, 0, 5, 3, 0> >_Pipeline_LOOP_GEN_WAVE' to 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_Pipeline_LOOP_GEN_WAVE'.
WARNING: [SYN 201-103] Legalizing function name 'PWM_gen_wave<ap_ufixed<16, 0, 5, 3, 0> >' to 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_s'.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_Pipeline_LOOP_GEN_WAVE' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'LOOP_GEN_WAVE'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'LOOP_GEN_WAVE'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.07 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.09 seconds; current allocated memory: 435.988 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 435.988 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_s' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 435.988 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 435.988 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'hls_pwm_gen' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.01 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.01 seconds; current allocated memory: 435.988 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 435.988 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_Pipeline_LOOP_GEN_WAVE' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_Pipeline_LOOP_GEN_WAVE' pipeline 'LOOP_GEN_WAVE' pipeline type 'loop pipeline'
INFO: [RTGEN 206-100] Generating core module 'add_19ns_19ns_19_1_1': 2 instance(s).
INFO: [RTGEN 206-100] Generating core module 'mul_18ns_16ns_34_1_1': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_Pipeline_LOOP_GEN_WAVE'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 437.461 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_s' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Generating core module 'mul_18ns_20ns_37_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'udiv_28ns_32ns_32_32_seq_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'PWM_gen_wave_ap_ufixed_16_0_5_3_0_s'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.05 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.06 seconds; current allocated memory: 443.246 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'hls_pwm_gen' 
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_duty_ratio_a' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_duty_ratio_b' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_duty_ratio_c' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_h_a' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_h_b' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_h_c' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_l_a' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_l_b' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_l_c' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_sync_a' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_sync_b' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/strm_pwm_sync_c' to 'ap_fifo'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/pwm_args_pwm_freq' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/pwm_args_dead_cycles' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/pwm_args_phase_shift' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/pwm_stt_pwm_cycle' to 's_axilite & ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/pwm_args_sample_ii' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/pwm_stt_duty_ratio_a' to 's_axilite & ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/pwm_stt_duty_ratio_b' to 's_axilite & ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on port 'hls_pwm_gen/pwm_stt_duty_ratio_c' to 's_axilite & ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on function 'hls_pwm_gen' to 's_axilite & ap_ctrl_hs'.
WARNING: [RTGEN 206-101] Register 'pwm_args_cnt_trip_constprop' is power-on initialization.
INFO: [RTGEN 206-100] Bundling port 'pwm_args_pwm_freq', 'pwm_args_dead_cycles', 'pwm_args_phase_shift', 'pwm_stt_pwm_cycle', 'pwm_args_sample_ii', 'pwm_stt_duty_ratio_a', 'pwm_stt_duty_ratio_b', 'pwm_stt_duty_ratio_c' and 'return' to AXI-Lite port pwm_args.
INFO: [RTGEN 206-100] Finished creating RTL model for 'hls_pwm_gen'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.03 seconds; current allocated memory: 444.105 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.1 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.11 seconds; current allocated memory: 447.359 MB.
INFO: [HLS 200-111] Finished Updating report files: CPU user time: 0.29 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.33 seconds; current allocated memory: 453.281 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for hls_pwm_gen.
INFO: [VLOG 209-307] Generating Verilog RTL for hls_pwm_gen.
INFO: [HLS 200-789] **** Estimated Fmax: 116.28 MHz
INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 00:00:10; Allocated memory: 65.875 MB.
INFO: [HLS 200-1510] Running: config_export -ipname hls_pwm_gen 
INFO: [HLS 200-1510] Running: export_design -rtl verilog -format ip_catalog 
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.

****** Vivado v2025.1 (64-bit)
  **** SW Build 6140274 on Wed May 21 22:58:25 MDT 2025
  **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025
  **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025
  **** Start of session at: Sun Jul 13 14:57:54 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
INFO: calling package_hls_ip ip_types=vitis sysgen json_file=/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/sol1_data.json outdir=/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/impl/ip srcdir=/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1 ippack_options_dict= ippack_options_dict=
INFO: Copied 1 ipmisc file(s) to /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/impl/ip/misc
INFO: Copied 14 verilog file(s) to /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/impl/ip/hdl/verilog
INFO: Copied 10 vhdl file(s) to /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/impl/ip/hdl/vhdl
INFO: Copied 10 swdriver file(s) to /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/impl/ip/drivers
INFO: Import ports from HDL: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/impl/ip/hdl/vhdl/hls_pwm_gen.vhd (hls_pwm_gen)
INFO: Add axi4lite interface s_axi_pwm_args
INFO: Add clock interface ap_clk
INFO: Add reset interface ap_rst_n
INFO: Add interrupt interface interrupt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.1/Vivado/data/ip'.
INFO: Add axi4stream interface strm_duty_ratio_a
INFO: Add axi4stream interface strm_duty_ratio_b
INFO: Add axi4stream interface strm_duty_ratio_c
INFO: Add ap_fifo interface strm_pwm_h_a
INFO: Add ap_fifo interface strm_pwm_h_b
INFO: Add ap_fifo interface strm_pwm_h_c
INFO: Add ap_fifo interface strm_pwm_l_a
INFO: Add ap_fifo interface strm_pwm_l_b
INFO: Add ap_fifo interface strm_pwm_l_c
INFO: Add ap_fifo interface strm_pwm_sync_a
INFO: Add ap_fifo interface strm_pwm_sync_b
INFO: Add ap_fifo interface strm_pwm_sync_c
INFO: Calling post_process_vitis to specialize IP
INFO: Calling post_process_sysgen to specialize IP
Generating sysgen info xml from json file
INFO: Created IP /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/impl/ip/component.xml
INFO: Created IP archive /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen/ip_pwm_gen.prj/sol1/impl/ip/xilinx_com_hls_hls_pwm_gen_1_0.zip
INFO: [Common 17-206] Exiting Vivado at Sun Jul 13 14:57:57 2025...
INFO: [HLS 200-802] Generated output file ip_pwm_gen.prj/sol1/impl/export.zip
INFO: [HLS 200-2161] Finished Command export_design Elapsed time: 00:00:09; Allocated memory: 4.098 MB.
INFO: [HLS 200-112] Total CPU user time: 12.06 seconds. Total CPU system time: 2.02 seconds. Total elapsed time: 20.77 seconds; peak allocated memory: 457.379 MB.
INFO: [vitis-run 60-791] Total elapsed time: 0h 0m 21s
INFO: [vitis-run 60-1662] Stopping dispatch session having empty uuid.
make[1]: Leaving directory '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/pwm_gen'
/tools/Xilinx/2025.1/Vivado/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8

****** Vivado v2025.1 (64-bit)
  **** SW Build 6140274 on Wed May 21 22:58:25 MDT 2025
  **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025
  **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025
  **** Start of session at: Sun Jul 13 14:58:04 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

source scripts/main.tcl -notrace
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:scu35:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/scu35/1.0/board.xml as part xcsu35p-sbvb625-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:v80:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/v80/1.0/board.xml as part xcv80-lsva4737-2mhp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.2/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.3/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.2/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:scu35:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/scu35/1.0/board.xml as part xcsu35p-sbvb625-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:v80:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/v80/1.0/board.xml as part xcv80-lsva4737-2mhp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.2/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.3 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.3/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.2 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.2/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/2025.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Definition IP file 'User:interface:data_valid:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_hub/interface/data_valid.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Abstraction IP file 'User:interface:data_valid_rtl:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid_rtl.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_hub/interface/data_valid_rtl.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Definition IP file 'User:interface:data_valid:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc7352_if/interface/data_valid.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Abstraction IP file 'User:interface:data_valid_rtl:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid_rtl.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc7352_if/interface/data_valid_rtl.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Definition IP file 'User:interface:data_valid:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_usb2btc/interface/data_valid.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Abstraction IP file 'User:interface:data_valid_rtl:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid_rtl.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_usb2btc/interface/data_valid_rtl.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Definition IP file 'User:interface:data_valid:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_bob2btc/interface/data_valid.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Abstraction IP file 'User:interface:data_valid_rtl:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid_rtl.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_bob2btc/interface/data_valid_rtl.xml
INFO: [IP_Flow 19-1700] Loaded user IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.1/Vivado/data/ip'.
Wrote  : </media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.srcs/sources_1/bd/kd240_bist/kd240_bist.bd> 
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'C_S_AXI4_ID_WIDTH' of cell '/axi_quad_spi_0' is ignored
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs eth_buf/S_AXI_2TEMAC/SEG_mac_Reg'
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs s_axi/SEG_eth_buf_REG'
WARNING: [BD 41-2721] Requested assignment from slave segment '/mac/s_axi/Reg' to address space '/eth_buf/S_AXI_2TEMAC' was auto-corrected from <0x0000_0000 [ 128K ]> to <0x0000_0000 [ 4K ]>.
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs eth_buf/S_AXI_2TEMAC/SEG_mac_Reg'
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs s_axi/SEG_eth_buf_REG'
WARNING: [BD 41-2721] Requested assignment from slave segment '/mac/s_axi/Reg' to address space '/eth_buf/S_AXI_2TEMAC' was auto-corrected from <0x0000_0000 [ 128K ]> to <0x0000_0000 [ 4K ]>.
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs eth_buf/S_AXI_2TEMAC/SEG_mac_Reg'
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs s_axi/SEG_eth_buf_REG'
WARNING: [BD 41-2721] Requested assignment from slave segment '/mac/s_axi/Reg' to address space '/eth_buf/S_AXI_2TEMAC' was auto-corrected from <0x0000_0000 [ 128K ]> to <0x0000_0000 [ 4K ]>.
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs eth_buf/S_AXI_2TEMAC/SEG_mac_Reg'
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs s_axi/SEG_eth_buf_REG'
WARNING: [BD 41-2721] Requested assignment from slave segment '/mac/s_axi/Reg' to address space '/eth_buf/S_AXI_2TEMAC' was auto-corrected from <0x0000_0000 [ 128K ]> to <0x0000_0000 [ 4K ]>.
INFO: [Device 21-403] Loading part xck24-ubva530-2LV-c
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilconcat:1.0 for the IP type xilinx.com:ip:xlconcat:2.1 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlconcat:2.1 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilconcat:1.0 for the IP type xilinx.com:ip:xlconcat:2.1 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlconcat:2.1 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilconcat:1.0 for the IP type xilinx.com:ip:xlconcat:2.1 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlconcat:2.1 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change 
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilslice:1.0 for the IP type xilinx.com:ip:xlslice:1.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlslice:1.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilconcat:1.0 for the IP type xilinx.com:ip:xlconcat:2.1 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlconcat:2.1 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilconstant:1.0 for the IP type xilinx.com:ip:xlconstant:1.1 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlconstant:1.1 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilvector_logic:1.0 for the IP type xilinx.com:ip:util_vector_logic:2.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:util_vector_logic:2.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'C_S_AXI4_ID_WIDTH' of cell '/axi_quad_spi_CAN' is ignored
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilvector_logic:1.0 for the IP type xilinx.com:ip:util_vector_logic:2.0 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:util_vector_logic:2.0 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
INFO: [BD 5-1043] It is recommended to use inline hdl version xilinx.com:inline_hdl:ilconstant:1.0 for the IP type xilinx.com:ip:xlconstant:1.1 for improved performance and reduced disk space. IPs with VLNV xilinx.com:ip:xlconstant:1.1 will not be supported from release 2025.2. More information on inline hdl IP is available in UG994 
WARNING: [BD 41-1306] The connection to interface pin </hls_qei_0/qei_A_dout> is being overridden by the user with net <A_0_1>. This pin will not be connected as a part of interface connection <qei_A>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_qei_0/qei_B_dout> is being overridden by the user with net <B_0_1>. This pin will not be connected as a part of interface connection <qei_B>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_qei_0/qei_I_dout> is being overridden by the user with net <I_0_1>. This pin will not be connected as a part of interface connection <qei_I>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </axi_quad_spi_0/io1_i> is being overridden by the user with net <TQ_SDO_1>. This pin will not be connected as a part of interface connection <SPI_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </axi_quad_spi_0/io0_o> is being overridden by the user with net <axi_quad_spi_0_io0_o>. This pin will not be connected as a part of interface connection <SPI_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </axi_quad_spi_0/sck_o> is being overridden by the user with net <axi_quad_spi_0_sck_o>. This pin will not be connected as a part of interface connection <SPI_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </axi_quad_spi_0/ss_o> is being overridden by the user with net <axi_quad_spi_0_ss_o>. This pin will not be connected as a part of interface connection <SPI_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </axi_quad_spi_CAN/io0_o> is being overridden by the user with net <axi_quad_spi_1_io0_o>. This pin will not be connected as a part of interface connection <SPI_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </axi_quad_spi_CAN/sck_o> is being overridden by the user with net <axi_quad_spi_1_sck_o>. This pin will not be connected as a part of interface connection <SPI_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </axi_quad_spi_CAN/ss_o> is being overridden by the user with net <axi_quad_spi_1_ss_o>. This pin will not be connected as a part of interface connection <SPI_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_pwm_gen_0/strm_pwm_h_a_din> is being overridden by the user with net <hls_pwm_gen_0_strm_pwm_h_a_din>. This pin will not be connected as a part of interface connection <strm_pwm_h_a>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_pwm_gen_0/strm_pwm_h_b_din> is being overridden by the user with net <hls_pwm_gen_0_strm_pwm_h_b_din>. This pin will not be connected as a part of interface connection <strm_pwm_h_b>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_pwm_gen_0/strm_pwm_h_c_din> is being overridden by the user with net <hls_pwm_gen_0_strm_pwm_h_c_din>. This pin will not be connected as a part of interface connection <strm_pwm_h_c>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_pwm_gen_0/strm_pwm_l_a_din> is being overridden by the user with net <hls_pwm_gen_0_strm_pwm_l_a_din>. This pin will not be connected as a part of interface connection <strm_pwm_l_a>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_pwm_gen_0/strm_pwm_l_b_din> is being overridden by the user with net <hls_pwm_gen_0_strm_pwm_l_b_din>. This pin will not be connected as a part of interface connection <strm_pwm_l_b>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_pwm_gen_0/strm_pwm_l_c_din> is being overridden by the user with net <hls_pwm_gen_0_strm_pwm_l_c_din>. This pin will not be connected as a part of interface connection <strm_pwm_l_c>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </hls_pwm_gen_0/strm_pwm_sync_a_din> is being overridden by the user with net <hls_pwm_gen_0_strm_pwm_sync_a_din>. This pin will not be connected as a part of interface connection <strm_pwm_sync_a>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
WARNING: [BD 41-1306] The connection to interface pin </axi_quad_spi_CAN/io1_i> is being overridden by the user with net <io1_i_0_1>. This pin will not be connected as a part of interface connection <SPI_0>, and might not recreate the connectivity as expected using the writ_bd_tcl command.
Slave segment '/ADC/adc_hub_phase_dc/S_AXI/Reg' is being assigned into address space '/PS_0/Data' at <0xA001_0000 [ 64K ]>.
Slave segment '/ethernet_subsystem/axi_dma_gem1/S_AXI_LITE/Reg' is being assigned into address space '/PS_0/Data' at <0x8001_0000 [ 64K ]>.
Slave segment '/ethernet_subsystem/axi_dma_gem2/S_AXI_LITE/Reg' is being assigned into address space '/PS_0/Data' at <0x8000_0000 [ 64K ]>.
Slave segment '/ethernet_subsystem/axi_ethernet_gem1/s_axi/Reg0' is being assigned into address space '/PS_0/Data' at <0x8008_0000 [ 256K ]>.
Slave segment '/ethernet_subsystem/axi_ethernet_gem2/s_axi/Reg0' is being assigned into address space '/PS_0/Data' at <0x8004_0000 [ 256K ]>.
Slave segment '/axi_gpio_0/S_AXI/Reg' is being assigned into address space '/PS_0/Data' at <0xA007_0000 [ 64K ]>.
Slave segment '/axi_quad_spi_0/AXI_LITE/Reg' is being assigned into address space '/PS_0/Data' at <0xA006_0000 [ 64K ]>.
Slave segment '/axi_quad_spi_CAN/AXI_LITE/Reg' is being assigned into address space '/PS_0/Data' at <0xA008_0000 [ 64K ]>.
Slave segment '/hls_foc_periodic_0/s_axi_foc_args/Reg' is being assigned into address space '/PS_0/Data' at <0xA000_0000 [ 64K ]>.
Slave segment '/hls_pwm_gen_0/s_axi_pwm_args/Reg' is being assigned into address space '/PS_0/Data' at <0xA004_0000 [ 64K ]>.
Slave segment '/hls_qei_0/s_axi_qei_args/Reg' is being assigned into address space '/PS_0/Data' at <0xA003_0000 [ 64K ]>.
Slave segment '/hls_svpwm_duty_0/s_axi_pwm_args/Reg' is being assigned into address space '/PS_0/Data' at <0xA005_0000 [ 64K ]>.
Slave segment '/motor_control_0/s_axi_cntrl/reg0' is being assigned into address space '/PS_0/Data' at <0xA002_0000 [ 4K ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/ethernet_subsystem/axi_dma_gem2/Data_MM2S' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/ethernet_subsystem/axi_dma_gem2/Data_S2MM' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/ethernet_subsystem/axi_dma_gem2/Data_SG' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/ethernet_subsystem/axi_dma_gem1/Data_MM2S' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/ethernet_subsystem/axi_dma_gem1/Data_S2MM' at <0x0000_0000 [ 2G ]>.
Slave segment '/PS_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/ethernet_subsystem/axi_dma_gem1/Data_SG' at <0x0000_0000 [ 2G ]>.
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change 
INFO: [xilinx.com:ip:c_shift_ram:12.0-913] /c_shift_ram_0 Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/ethernet_subsystem/axi_smc/S00_AXI' to master interface '/ethernet_subsystem/axi_smc/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/ethernet_subsystem/axi_smc/S01_AXI' to master interface '/ethernet_subsystem/axi_smc/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/ethernet_subsystem/axi_smc/S02_AXI' to master interface '/ethernet_subsystem/axi_smc/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/ethernet_subsystem/axi_smc/S03_AXI' to master interface '/ethernet_subsystem/axi_smc/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/ethernet_subsystem/axi_smc/S04_AXI' to master interface '/ethernet_subsystem/axi_smc/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/ethernet_subsystem/axi_smc/S05_AXI' to master interface '/ethernet_subsystem/axi_smc/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [xilinx.com:ip:smartconnect:1.0-1] kd240_bist_axi_smc_0: SmartConnect kd240_bist_axi_smc_0 is in High-performance Mode.
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_quad_spi_0 
                   #######################################################################################
                   INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
                   ########################################################################################
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /ethernet_subsystem/clk_wiz_1 clk_wiz propagate
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /ethernet_subsystem/clk_wiz clk_wiz propagate
INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /axi_quad_spi_CAN 
                   #######################################################################################
                   INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other.
                   ########################################################################################
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate
WARNING: [BD 41-926] Following properties on interface pin /motor_control_0/s_axis_phase_c_i have been updated from connected ip, but BD cell '/motor_control_0' does not accept parameter changes, so they may not be synchronized with cell properties:
	TDATA_NUM_BYTES = 3

Please resolve any mismatches by directly setting properties on BD cell </motor_control_0> to completely resolve these warnings.
WARNING: [BD 41-926] Following properties on interface pin /motor_control_0/s_axis_phase_a_i have been updated from connected ip, but BD cell '/motor_control_0' does not accept parameter changes, so they may not be synchronized with cell properties:
	TDATA_NUM_BYTES = 3

Please resolve any mismatches by directly setting properties on BD cell </motor_control_0> to completely resolve these warnings.
WARNING: [BD 41-926] Following properties on interface pin /motor_control_0/s_axis_phase_b_i have been updated from connected ip, but BD cell '/motor_control_0' does not accept parameter changes, so they may not be synchronized with cell properties:
	TDATA_NUM_BYTES = 3

Please resolve any mismatches by directly setting properties on BD cell </motor_control_0> to completely resolve these warnings.
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect_cntrl/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM0_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect_cntrl/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM0_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ethernet_subsystem/axi_interconnect_0/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM0_LPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ethernet_subsystem/axi_interconnect_0/s00_couplers/auto_pc/S_AXI(0) and /PS_0/M_AXI_HPM0_LPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /PS_0/S_AXI_HP0_FPD(1) and /ethernet_subsystem/axi_smc/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /PS_0/S_AXI_HP0_FPD(1) and /ethernet_subsystem/axi_smc/M00_AXI(0)
Wrote  : </media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.srcs/sources_1/bd/kd240_bist/kd240_bist.bd> 
INFO: [BD 41-1662] The design 'kd240_bist.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/sim/kd240_bist.v
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/hdl/kd240_bist_wrapper.v
INFO: [Project 1-1716] Could not find the wrapper file ./project/kd240_bist.srcs/sources_1/bd/kd240_bist/hdl/kd240_bist_wrapper.v, checking in project .gen location instead.
INFO: [Vivado 12-12391] Found file ./project/kd240_bist.gen/sources_1/bd/kd240_bist/hdl/kd240_bist_wrapper.v, importing it to Project
INFO: [BD 5-320] Validate design is not run, since the design is already validated.
INFO: [BD 41-1662] The design 'kd240_bist.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/sim/kd240_bist.v
Verilog Output written to : /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/hdl/kd240_bist_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_cntrl/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axi_interconnect_cntrl_imp_auto_pc_0/kd240_bist_axi_interconnect_cntrl_imp_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_cntrl/s00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_quad_spi_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/axi_dma_gem2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/axi_dma_gem1 .
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axi_ethernet_gem2_0/bd_0/hw_handoff/kd240_bist_axi_ethernet_gem2_0.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axi_ethernet_gem2_0/bd_0/synth/kd240_bist_axi_ethernet_gem2_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/axi_ethernet_gem2 .
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axi_ethernet_gem1_0/bd_0/hw_handoff/kd240_bist_axi_ethernet_gem1_0.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axi_ethernet_gem1_0/bd_0/synth/kd240_bist_axi_ethernet_gem1_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/axi_ethernet_gem1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/axi_interconnect_0/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axi_interconnect_0_imp_auto_pc_0/kd240_bist_axi_interconnect_0_imp_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/axi_interconnect_0/s00_couplers/auto_pc .
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axi_smc_0/bd_0/hw_handoff/kd240_bist_axi_smc_0.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axi_smc_0/bd_0/synth/kd240_bist_axi_smc_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/axi_smc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/clk_wiz .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/clk_wiz_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/proc_sys_reset_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ethernet_subsystem/xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gate_driver/gate_driver_A .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gate_driver/gate_driver_B .
INFO: [BD 41-1029] Generation completed for the IP Integrator block gate_driver/gate_driver_C .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hls_pwm_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hls_qei_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hls_svpwm_duty_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_int .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlslice_fan .
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.5-0] kd240_bist_PS_0_0: 
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Amd's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Amd's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_FPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_LPD'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0_FPD'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block PS_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hls_foc_periodic_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axis_broadcaster_0_0/kd240_bist_axis_broadcaster_0_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block broadcast_i/axis_broadcaster_0 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axis_broadcaster_1_0/kd240_bist_axis_broadcaster_1_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block broadcast_i/axis_broadcaster_1 .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_axis_broadcaster_2_0/kd240_bist_axis_broadcaster_2_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block broadcast_i/axis_broadcaster_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block motor_control_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/adc_hub_phase_dc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/adc_if .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/adc_usb2btc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/adc_bob2btc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/adc_sample_ctrl_dc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/adc_sample_ctrl_motor .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_CSn .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_dc_CSn .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_oc_err_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_oc_err_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_oc_err_5 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_oc_err_7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_ov_err_6 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_uc_err_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_uc_err_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_uc_err_5 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_uc_err_7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/slices/xlslice_uv_err_6 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync/dc_csn_sync .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync/dc_update_sync .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync/motor_csn_sync .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync/motor_update_sync .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync/sclk_resetn_sync .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync_vector/synchronizer_vector_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync_vector/synchronizer_vector_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync_vector/synchronizer_vector_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync_vector/synchronizer_vector_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync_vector/synchronizer_vector_4 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync_vector/synchronizer_vector_5 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync_vector/synchronizer_vector_6 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/sync_vector/synchronizer_vector_7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/xlconcat_update .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ADC/xlconstant_gnd .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_quad_spi_CAN .
INFO: [BD 41-1029] Generation completed for the IP Integrator block invert_can_int .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconstant_can_rstn .
Exporting to file /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/hw_handoff/kd240_bist.hwh
Generated Hardware Definition File /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.hwdef
generate_target: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 3391.812 ; gain = 0.000 ; free physical = 42492 ; free virtual = 71490
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Sun Jul 13 14:58:38 2025] Launched bd_1975_c_counter_binary_0_0_synth_1, kd240_bist_hls_pwm_gen_0_0_synth_1, bd_1985_c_counter_binary_0_0_synth_1, kd240_bist_gate_driver_B_0_synth_1, kd240_bist_proc_sys_reset_1_0_synth_1, kd240_bist_hls_qei_0_0_synth_1, kd240_bist_gate_driver_C_0_synth_1, kd240_bist_hls_svpwm_duty_0_0_synth_1, kd240_bist_axi_ethernet_gem2_0_synth_1, kd240_bist_proc_sys_reset_0_1_synth_1, bd_1985_eth_buf_0_synth_1, kd240_bist_proc_sys_reset_0_0_synth_1, kd240_bist_clk_wiz_1_0_synth_1, bd_1985_c_shift_ram_0_0_synth_1, bd_1985_util_vector_logic_0_0_synth_1, bd_1975_c_shift_ram_0_0_synth_1, bd_1975_util_vector_logic_0_0_synth_1, kd240_bist_gate_driver_A_0_synth_1, bd_1985_mac_0_synth_1, bd_1975_eth_buf_0_synth_1, kd240_bist_axi_ethernet_gem1_0_synth_1, kd240_bist_adc_bob2btc_0_synth_1, kd240_bist_axis_broadcaster_0_0_synth_1, kd240_bist_adc_usb2btc_0_synth_1, kd240_bist_PS_0_0_synth_1, kd240_bist_axi_interconnect_cntrl_imp_xbar_0_synth_1, kd240_bist_axi_quad_spi_0_0_synth_1, kd240_bist_synchronizer_vector_7_0_synth_1, kd240_bist_synchronizer_vector_0_0_synth_1, kd240_bist_axi_dma_gem2_0_synth_1, kd240_bist_adc_if_0_synth_1, kd240_bist_synchronizer_vector_6_0_synth_1, kd240_bist_axi_interconnect_cntrl_imp_auto_pc_0_synth_1, kd240_bist_adc_hub_phase_dc_0_synth_1, kd240_bist_invert_can_int_0_synth_1, kd240_bist_sclk_resetn_sync_0_synth_1, kd240_bist_synchronizer_vector_1_0_synth_1, kd240_bist_synchronizer_vector_4_0_synth_1, kd240_bist_synchronizer_vector_2_0_synth_1, kd240_bist_axi_dma_gem1_0_synth_1, kd240_bist_clk_wiz_0_0_synth_1, kd240_bist_clk_wiz_0_synth_1, kd240_bist_axi_gpio_0_0_synth_1, kd240_bist_adc_sample_ctrl_motor_0_synth_1, kd240_bist_axi_smc_0_synth_1, kd240_bist_synchronizer_vector_5_0_synth_1, kd240_bist_adc_sample_ctrl_dc_0_synth_1, kd240_bist_util_vector_logic_0_0_synth_1, kd240_bist_synchronizer_vector_3_0_synth_1, bd_1975_mac_0_synth_1, kd240_bist_motor_control_0_0_synth_1, kd240_bist_axi_interconnect_0_imp_auto_pc_0_synth_1, kd240_bist_dc_csn_sync_0_synth_1, kd240_bist_motor_csn_sync_0_synth_1, kd240_bist_motor_update_sync_0_synth_1, kd240_bist_axi_quad_spi_CAN_0_synth_1, kd240_bist_axi_interconnect_0_imp_xbar_0_synth_1, kd240_bist_axis_broadcaster_2_0_synth_1, kd240_bist_axis_broadcaster_1_0_synth_1, kd240_bist_hls_foc_periodic_0_0_synth_1, kd240_bist_dc_update_sync_0_synth_1...
Run output will be captured here:
bd_1975_c_counter_binary_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1975_c_counter_binary_0_0_synth_1/runme.log
kd240_bist_hls_pwm_gen_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_hls_pwm_gen_0_0_synth_1/runme.log
bd_1985_c_counter_binary_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1985_c_counter_binary_0_0_synth_1/runme.log
kd240_bist_gate_driver_B_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_gate_driver_B_0_synth_1/runme.log
kd240_bist_proc_sys_reset_1_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_proc_sys_reset_1_0_synth_1/runme.log
kd240_bist_hls_qei_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_hls_qei_0_0_synth_1/runme.log
kd240_bist_gate_driver_C_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_gate_driver_C_0_synth_1/runme.log
kd240_bist_hls_svpwm_duty_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_hls_svpwm_duty_0_0_synth_1/runme.log
kd240_bist_axi_ethernet_gem2_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_ethernet_gem2_0_synth_1/runme.log
kd240_bist_proc_sys_reset_0_1_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_proc_sys_reset_0_1_synth_1/runme.log
bd_1985_eth_buf_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1985_eth_buf_0_synth_1/runme.log
kd240_bist_proc_sys_reset_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_proc_sys_reset_0_0_synth_1/runme.log
kd240_bist_clk_wiz_1_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_clk_wiz_1_0_synth_1/runme.log
bd_1985_c_shift_ram_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1985_c_shift_ram_0_0_synth_1/runme.log
bd_1985_util_vector_logic_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1985_util_vector_logic_0_0_synth_1/runme.log
bd_1975_c_shift_ram_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1975_c_shift_ram_0_0_synth_1/runme.log
bd_1975_util_vector_logic_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1975_util_vector_logic_0_0_synth_1/runme.log
kd240_bist_gate_driver_A_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_gate_driver_A_0_synth_1/runme.log
bd_1985_mac_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1985_mac_0_synth_1/runme.log
bd_1975_eth_buf_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1975_eth_buf_0_synth_1/runme.log
kd240_bist_axi_ethernet_gem1_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_ethernet_gem1_0_synth_1/runme.log
kd240_bist_adc_bob2btc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_adc_bob2btc_0_synth_1/runme.log
kd240_bist_axis_broadcaster_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axis_broadcaster_0_0_synth_1/runme.log
kd240_bist_adc_usb2btc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_adc_usb2btc_0_synth_1/runme.log
kd240_bist_PS_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_PS_0_0_synth_1/runme.log
kd240_bist_axi_interconnect_cntrl_imp_xbar_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_interconnect_cntrl_imp_xbar_0_synth_1/runme.log
kd240_bist_axi_quad_spi_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_quad_spi_0_0_synth_1/runme.log
kd240_bist_synchronizer_vector_7_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_synchronizer_vector_7_0_synth_1/runme.log
kd240_bist_synchronizer_vector_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_synchronizer_vector_0_0_synth_1/runme.log
kd240_bist_axi_dma_gem2_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_dma_gem2_0_synth_1/runme.log
kd240_bist_adc_if_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_adc_if_0_synth_1/runme.log
kd240_bist_synchronizer_vector_6_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_synchronizer_vector_6_0_synth_1/runme.log
kd240_bist_axi_interconnect_cntrl_imp_auto_pc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_interconnect_cntrl_imp_auto_pc_0_synth_1/runme.log
kd240_bist_adc_hub_phase_dc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_adc_hub_phase_dc_0_synth_1/runme.log
kd240_bist_invert_can_int_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_invert_can_int_0_synth_1/runme.log
kd240_bist_sclk_resetn_sync_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_sclk_resetn_sync_0_synth_1/runme.log
kd240_bist_synchronizer_vector_1_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_synchronizer_vector_1_0_synth_1/runme.log
kd240_bist_synchronizer_vector_4_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_synchronizer_vector_4_0_synth_1/runme.log
kd240_bist_synchronizer_vector_2_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_synchronizer_vector_2_0_synth_1/runme.log
kd240_bist_axi_dma_gem1_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_dma_gem1_0_synth_1/runme.log
kd240_bist_clk_wiz_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_clk_wiz_0_0_synth_1/runme.log
kd240_bist_clk_wiz_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_clk_wiz_0_synth_1/runme.log
kd240_bist_axi_gpio_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_gpio_0_0_synth_1/runme.log
kd240_bist_adc_sample_ctrl_motor_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_adc_sample_ctrl_motor_0_synth_1/runme.log
kd240_bist_axi_smc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_smc_0_synth_1/runme.log
kd240_bist_synchronizer_vector_5_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_synchronizer_vector_5_0_synth_1/runme.log
kd240_bist_adc_sample_ctrl_dc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_adc_sample_ctrl_dc_0_synth_1/runme.log
kd240_bist_util_vector_logic_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_util_vector_logic_0_0_synth_1/runme.log
kd240_bist_synchronizer_vector_3_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_synchronizer_vector_3_0_synth_1/runme.log
bd_1975_mac_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/bd_1975_mac_0_synth_1/runme.log
kd240_bist_motor_control_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_motor_control_0_0_synth_1/runme.log
kd240_bist_axi_interconnect_0_imp_auto_pc_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_interconnect_0_imp_auto_pc_0_synth_1/runme.log
kd240_bist_dc_csn_sync_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_dc_csn_sync_0_synth_1/runme.log
kd240_bist_motor_csn_sync_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_motor_csn_sync_0_synth_1/runme.log
kd240_bist_motor_update_sync_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_motor_update_sync_0_synth_1/runme.log
kd240_bist_axi_quad_spi_CAN_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_quad_spi_CAN_0_synth_1/runme.log
kd240_bist_axi_interconnect_0_imp_xbar_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axi_interconnect_0_imp_xbar_0_synth_1/runme.log
kd240_bist_axis_broadcaster_2_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axis_broadcaster_2_0_synth_1/runme.log
kd240_bist_axis_broadcaster_1_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_axis_broadcaster_1_0_synth_1/runme.log
kd240_bist_hls_foc_periodic_0_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_hls_foc_periodic_0_0_synth_1/runme.log
kd240_bist_dc_update_sync_0_synth_1: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/kd240_bist_dc_update_sync_0_synth_1/runme.log
[Sun Jul 13 14:58:38 2025] Launched synth_1...
Run output will be captured here: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/runme.log
[Sun Jul 13 14:58:38 2025] Waiting for synth_1 to finish...

*** Running vivado
    with args -log kd240_bist_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source kd240_bist_wrapper.tcl


****** Vivado v2025.1 (64-bit)
  **** SW Build 6140274 on Wed May 21 22:58:25 MDT 2025
  **** IP Build 6138677 on Thu May 22 03:10:11 MDT 2025
  **** SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025
  **** Start of session at: Sun Jul 13 15:02:39 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

source kd240_bist_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Definition IP file 'User:interface:data_valid:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_hub/interface/data_valid.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Abstraction IP file 'User:interface:data_valid_rtl:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid_rtl.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_hub/interface/data_valid_rtl.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Definition IP file 'User:interface:data_valid:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc7352_if/interface/data_valid.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Abstraction IP file 'User:interface:data_valid_rtl:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid_rtl.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc7352_if/interface/data_valid_rtl.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Definition IP file 'User:interface:data_valid:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_usb2btc/interface/data_valid.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Abstraction IP file 'User:interface:data_valid_rtl:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid_rtl.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_usb2btc/interface/data_valid_rtl.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Definition IP file 'User:interface:data_valid:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_bob2btc/interface/data_valid.xml
WARNING: [IP_Flow 19-1694] Ignoring duplicate Bus Abstraction IP file 'User:interface:data_valid_rtl:1.0' found within IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
File in use: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/synchronizer_vector_vld/interface/data_valid_rtl.xml
File ignored: /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip/adc_bob2btc/interface/data_valid_rtl.xml
INFO: [IP_Flow 19-1700] Loaded user IP repository '/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.1/Vivado/data/ip'.
INFO: [Project 1-5698] Found the below utility IPs instantiated in block design /media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.srcs/sources_1/bd/kd240_bist/kd240_bist.bd which have equivalent inline hdl with improved performance and reduced diskspace.
It is recommended to migrate these utility IPs to inline hdl  using the command upgrade_project -migrate_to_inline_hdl.  The utility IPs may be deprecated in future releases.
More information on inline hdl is available in UG994.
Utility IP Component Instances:
 kd240_bist_xlconcat_0_0
kd240_bist_xlconcat_0_1
kd240_bist_xlconcat_int_0
kd240_bist_xlslice_fan_0
kd240_bist_xlslice_CSn_0
kd240_bist_xlslice_dc_CSn_0
kd240_bist_xlslice_oc_err_1_0
kd240_bist_xlslice_oc_err_3_0
kd240_bist_xlslice_oc_err_5_0
kd240_bist_xlslice_oc_err_7_0
kd240_bist_xlslice_ov_err_6_0
kd240_bist_xlslice_uc_err_1_0
kd240_bist_xlslice_uc_err_3_0
kd240_bist_xlslice_uc_err_5_0
kd240_bist_xlslice_uc_err_7_0
kd240_bist_xlslice_uv_err_6_0
kd240_bist_xlconcat_update_0
kd240_bist_xlconstant_gnd_0
kd240_bist_util_vector_logic_0_0
kd240_bist_invert_can_int_0
kd240_bist_xlconstant_can_rstn_0
Command: synth_design -top kd240_bist_wrapper -part xck24-ubva530-2LV-c
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xck24'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xck24'
INFO: [Device 21-403] Loading part xck24-ubva530-2LV-c
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 212757
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2721.414 ; gain = 134.688 ; free physical = 40274 ; free virtual = 69546
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_wrapper' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.srcs/sources_1/imports/hdl/kd240_bist_wrapper.v:13]
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/tools/Xilinx/2025.1/Vivado/scripts/rt/data/unisim_comp.v:81434]
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/tools/Xilinx/2025.1/Vivado/scripts/rt/data/unisim_comp.v:81434]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:1842]
INFO: [Synth 8-6157] synthesizing module 'ADC_imp_1PSR3NS' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:13]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_adc_bob2btc_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_bob2btc_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_adc_bob2btc_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_bob2btc_0_stub.v:6]
WARNING: [Synth 8-7071] port 'L0_DOUT' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L0_DOUT_VLD' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L2_DOUT' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L2_DOUT_VLD' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L4_DOUT' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L4_DOUT_VLD' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L6_DOUT' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L6_DOUT_VLD' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L7_DOUT' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7071] port 'L7_DOUT_VLD' of module 'kd240_bist_adc_bob2btc_0' is unconnected for instance 'adc_bob2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
WARNING: [Synth 8-7023] instance 'adc_bob2btc' of module 'kd240_bist_adc_bob2btc_0' has 34 connections declared, but only 24 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:237]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_adc_hub_phase_dc_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_hub_phase_dc_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_adc_hub_phase_dc_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_hub_phase_dc_0_stub.v:6]
WARNING: [Synth 8-7071] port 'L0_axis_tdata' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L0_axis_tlast' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L0_axis_tvalid' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L2_axis_tdata' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L2_axis_tlast' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L2_axis_tvalid' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L4_axis_tdata' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L4_axis_tlast' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L4_axis_tvalid' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L6_axis_tlast' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L7_axis_tdata' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L7_axis_tlast' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7071] port 'L7_axis_tvalid' of module 'kd240_bist_adc_hub_phase_dc_0' is unconnected for instance 'adc_hub_phase_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
WARNING: [Synth 8-7023] instance 'adc_hub_phase_dc' of module 'kd240_bist_adc_hub_phase_dc_0' has 72 connections declared, but only 59 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:262]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_adc_if_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_if_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_adc_if_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_if_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_adc_sample_ctrl_dc_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_sample_ctrl_dc_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_adc_sample_ctrl_dc_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_sample_ctrl_dc_0_stub.v:6]
WARNING: [Synth 8-7071] port 'status' of module 'kd240_bist_adc_sample_ctrl_dc_0' is unconnected for instance 'adc_sample_ctrl_dc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:344]
WARNING: [Synth 8-7023] instance 'adc_sample_ctrl_dc' of module 'kd240_bist_adc_sample_ctrl_dc_0' has 7 connections declared, but only 6 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:344]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_adc_sample_ctrl_motor_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_sample_ctrl_motor_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_adc_sample_ctrl_motor_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_sample_ctrl_motor_0_stub.v:6]
WARNING: [Synth 8-7071] port 'status' of module 'kd240_bist_adc_sample_ctrl_motor_0' is unconnected for instance 'adc_sample_ctrl_motor' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:351]
WARNING: [Synth 8-7023] instance 'adc_sample_ctrl_motor' of module 'kd240_bist_adc_sample_ctrl_motor_0' has 7 connections declared, but only 6 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:351]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_adc_usb2btc_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_usb2btc_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_adc_usb2btc_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_adc_usb2btc_0_stub.v:6]
WARNING: [Synth 8-7071] port 'L1_DOUT' of module 'kd240_bist_adc_usb2btc_0' is unconnected for instance 'adc_usb2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:358]
WARNING: [Synth 8-7071] port 'L1_DOUT_VLD' of module 'kd240_bist_adc_usb2btc_0' is unconnected for instance 'adc_usb2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:358]
WARNING: [Synth 8-7071] port 'L3_DOUT' of module 'kd240_bist_adc_usb2btc_0' is unconnected for instance 'adc_usb2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:358]
WARNING: [Synth 8-7071] port 'L3_DOUT_VLD' of module 'kd240_bist_adc_usb2btc_0' is unconnected for instance 'adc_usb2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:358]
WARNING: [Synth 8-7071] port 'L5_DOUT' of module 'kd240_bist_adc_usb2btc_0' is unconnected for instance 'adc_usb2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:358]
WARNING: [Synth 8-7071] port 'L5_DOUT_VLD' of module 'kd240_bist_adc_usb2btc_0' is unconnected for instance 'adc_usb2btc' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:358]
WARNING: [Synth 8-7023] instance 'adc_usb2btc' of module 'kd240_bist_adc_usb2btc_0' has 34 connections declared, but only 28 given [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:358]
INFO: [Synth 8-6157] synthesizing module 'slices_imp_1SVCDLN' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:7223]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_CSn_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_CSn_0/synth/kd240_bist_xlslice_CSn_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_CSn_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_CSn_0/synth/kd240_bist_xlslice_CSn_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_dc_CSn_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_dc_CSn_0/synth/kd240_bist_xlslice_dc_CSn_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_dc_CSn_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_dc_CSn_0/synth/kd240_bist_xlslice_dc_CSn_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_oc_err_1_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_oc_err_1_0/synth/kd240_bist_xlslice_oc_err_1_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized1' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized1' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_oc_err_1_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_oc_err_1_0/synth/kd240_bist_xlslice_oc_err_1_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_oc_err_3_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_oc_err_3_0/synth/kd240_bist_xlslice_oc_err_3_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized2' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized2' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_oc_err_3_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_oc_err_3_0/synth/kd240_bist_xlslice_oc_err_3_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_oc_err_5_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_oc_err_5_0/synth/kd240_bist_xlslice_oc_err_5_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized3' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized3' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_oc_err_5_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_oc_err_5_0/synth/kd240_bist_xlslice_oc_err_5_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_oc_err_7_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_oc_err_7_0/synth/kd240_bist_xlslice_oc_err_7_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_oc_err_7_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_oc_err_7_0/synth/kd240_bist_xlslice_oc_err_7_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_ov_err_6_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_ov_err_6_0/synth/kd240_bist_xlslice_ov_err_6_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'xlslice_v1_0_5_xlslice__parameterized4' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'xlslice_v1_0_5_xlslice__parameterized4' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ipshared/6792/hdl/xlslice_v1_0_vl_rfs.v:58]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_ov_err_6_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_ov_err_6_0/synth/kd240_bist_xlslice_ov_err_6_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_uc_err_1_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uc_err_1_0/synth/kd240_bist_xlslice_uc_err_1_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_uc_err_1_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uc_err_1_0/synth/kd240_bist_xlslice_uc_err_1_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_uc_err_3_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uc_err_3_0/synth/kd240_bist_xlslice_uc_err_3_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_uc_err_3_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uc_err_3_0/synth/kd240_bist_xlslice_uc_err_3_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_uc_err_5_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uc_err_5_0/synth/kd240_bist_xlslice_uc_err_5_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_uc_err_5_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uc_err_5_0/synth/kd240_bist_xlslice_uc_err_5_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_uc_err_7_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uc_err_7_0/synth/kd240_bist_xlslice_uc_err_7_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_uc_err_7_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uc_err_7_0/synth/kd240_bist_xlslice_uc_err_7_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_xlslice_uv_err_6_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uv_err_6_0/synth/kd240_bist_xlslice_uv_err_6_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'kd240_bist_xlslice_uv_err_6_0' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/ip/kd240_bist_xlslice_uv_err_6_0/synth/kd240_bist_xlslice_uv_err_6_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 'slices_imp_1SVCDLN' (0#1) [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:7223]
INFO: [Synth 8-6157] synthesizing module 'sync_imp_EJD5IV' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.gen/sources_1/bd/kd240_bist/synth/kd240_bist.v:7309]
INFO: [Synth 8-6157] synthesizing module 'kd240_bist_dc_csn_sync_0' [/media/logictronix05/HDD05/krishna2025/test-2025-1/kria-vitis-platforms-1.0.1/kd240/platforms/kd240_bist/project/kd240_bist.runs/synth_1/.Xil/Vivado-212602-logictronix05-MS-7E26/realtime/kd240_bist_dc_csn_sync_0_stub.v:6]
...

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Credits

LogicTronix [FPGA Design + Machine Learning Company]

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We are Certified FPGA Design + Machine Learning-ML Acceleration Company offering design services on FPGA/ML, IP cores and edge-AI solutions.

KD240 BIST - Platform/App Recreating with 2025.1 Vitis & HLS

Things used in this project

Hardware components

Software apps and online services

Story

A. Overview

B. Steps performed:

C. Preparing Setup and Running BIST on KD240

Schematics

KD240 BIST VIVADO block design

Code

KD240-BIST-20251-build-log

Credits

LogicTronix [FPGA Design + Machine Learning Company]

Comments

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KD240 BIST - Platform/App Recreating with 2025.1 Vitis & HLS

KD240 BIST - Platform/App Recreating with 2025.1 Vitis & HLS

Things used in this project

Hardware components

Software apps and online services

Story

A. Overview

B. Steps performed:

C. Preparing Setup and Running BIST on KD240

Schematics

KD240 BIST VIVADO block design

Code

KD240-BIST-20251-build-log

Credits

LogicTronix [FPGA Design + Machine Learning Company]

Comments

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