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This tutorial is on how to create the DPU 3.0 TRD for ZCU106 FPGA Board. Although we already have published tutorials on DPU 3.0 TRD for ZCU104, DPU TRD for Ultra96 and other boards.
This tutorial is based on DPU IP version 3.0 which is been released at August 13, 2019. We used VIVADO and Petalinux 2019.1 version in this tutorial.
The detailed tutorial is linked at here [we skipped to copy from LogicTronix to here], please visit: DPU(3.0) TRD for ZCU106-LogicTronix.
Are you interested on Accelerating ML Application on ZCU106 with DPU?
We have developed ZCU106 based applications as "Yolov3 based object detection recognition" , "Vehicle counting" and "Social Distancing Detection" , "Lane detection", "License Plate Detection", "Pedestrian Detection" etc.
Picture on this tutorial is taken from BDD dataset and Xilinx ZCU106 Board image.
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We are Certified FPGA Design + Machine Learning-ML Acceleration Company offering design services on FPGA/ML, IP cores and edge-AI solutions.
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