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With a traditional processor, the hardware platform is pre-defined. The manufacturer selected the processor parameters and built-in peripherals when the chip was designed. To make use of this pre-defined processor, you need only target that specific hardware platform in the software development tools.
The Zynq® UltraScale+™ MPSoC is different. ZU+ provides multiple building blocks and leaves the definition to you as the design engineer. This adds flexibility, but it also means that a bit of work needs to be done up front before any software development can take place.
The first step in completing a ZU+ design is to define and build the hardware platform in the Vivado® Design Suite. The purpose of this tutorial is to show you how to quickly and easily create a base hardware platform for Ultra96.
Much of this project draws from the Xilinx Zynq UltraScale+ MPSoC Embedded Design Tutorial UG1209, adapted to the Ultra96-V2. It is highly recommended that the user refers to this document as well.Objectives
When this tutorial is complete, you will be able to:
- Create a new project in Vivado, targeting Ultra96 and the ZU+ MPSoC
- Create a block based design to insert an ARM processing system
- Import the Ultra96 Preset settings
- Build and export the hardware platform
The software used to test this reference design is:
- VirtualBox Ubuntu 18.04.1 Virtual Machine
- Xilinx Vivado 2020.2
- Board Definition File (BDF) Install from the Avnet BDF Repository on GitHub.
The hardware setup used to test this reference design includes:
- Host PC
- 96Boards 4A Power Supply
- Ultra96 JTAG/UART Pod
The Ultra96 development board is supported by Vivado WebPack (which is free). The Processing System (PS) may be used without anything programmed in the Programmable Logic (PL). This PS-only style is the simplest way to use Zynq, so that is what we will do during this lab. However, the power of ZU+ is found in using soft IP in the PL, interconnecting PS to PL, and routing extra PS built-in peripherals through EMIO to PL I/Os, and then programming of the PL is required.
This tutorial will take advantage Avnet's board definition files.
- Launch Vivado 2020.2
- Now follow the instructions in this blog to install and point to the Avnet board definition files:https://www.element14.com/community/groups/fpga-group/blog/2021/02/25/how-to-leverage-board-presets-to-accelerate-your-vivado-design
- Select File > Project > New or click on Create New Project under Quick Start.
Click Next >.
- Click the browse icon to the right of the Projectlocation. Browse to set the Project location to your desired project location and click Select. Set the Project name to Ultra96_Basic_System. Also verify the Create project subdirectory checkbox is selected. Click Next >.
- The project will be RTL based, so leave the radio button for RTL Project selected. Since this is a brand new project, check the box for Do not specify sources at this time. Click Next >.
Next, the Default Part is selected. This can be done by specifying a specific Xilinx part (Parts) or by selecting a board. If you have installed the Board Definition archive and set the Repo correctly, you will have access to the Ultra96 BDF.
- Select Boards.
- Set the Vendor to avnet.com (do not select em.avnet.com as that selection is now deprecated). Scroll until you find Ultra96-V2 SingleBoard Computer. The File Version can be either 1.1 or 1.2 (working on 1.2 now) and the Board Rev is irrelevant as all Revs (1, 2, and 4) are functionally equivalent.
- Single-click the line with Ultra96-V2 Click Next >.
- A project summary is displayed. Click Finish. The Vivado cockpit is now displayed.
The current project is blank. To access the ARM processing system, we will add an embedded source to the Vivado project using IP Integrator.
- The recommended way to add an embedded processor is through the Block Design method via IP Integrator. Select Create Block Design.
- Give the Block Design a name or use the default name of design_1. Click OK.
- In the Diagram window, click the Add IP text icon 📷 in either location.
- The Add IP window opens. Start typing “Zynq” in the search window. Find the ZYNQ UltraScale + MPSoC IP. Either double-click this or drag and drop to the Diagram window.
The ZU+ Processing System (PS or PS8) will appear in the Diagram window. Also two new tabs will appear labeled Address Editor and Address Map.
You may also see the following critical warning, which is a current bug in the Vivado tools and can be ignored.
CRITICAL WARNING: [PSU-1] Actual device frequency is : 479.995209. Minimum actual device frequency supported for DDR for current part is 500.000000.
- Similar to the Add IP prompt in the previous step, notice now that the Designer Assistance has provided the hint to Run Block Automation. Click the Run Block Automation link at the top of the window.
- The Apply Board Preset checkbox applies the Preset TCL that was included as part of the board definition archive. Leave this checked. Click OK.
You will now see an update to the ZU+ MPSoC block.
- The maxihpm* clocks must be connected. You can do this by clicking and dragging from the pl_clk0 pin to each maxihpmx_fpd_aclk pin, or you can run the commands below in the Tcl Console:
connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk]
connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/maxihpm1_fpd_aclk]
The other connections may be left disconnected for now.
- At this point, we can validate our design. Click the Validate Design icon. A successful validation window will appear. Click OK.
- Click Save Block Design icon, 📷, to save the project.
- Switch to the Sources tab by clicking on it.
- Left-click to expand Design Sources, and then right-click on design_1(design_1.bd) and select Create HDL wrapper.
- For now, leave the option selected to Let Vivado manage wrapper and auto-update. Click OK.
- Once the top-level wrapper is created, you can see the design hierarchy in the Sources tab. Notice that design_1_wrapper.v is the top-level HDL wrapper that was created. design_1.bd is the Block Design.
- Click GenerateBitstream in the Flow Navigator window.
- Click yes to start Synthesis and Implementation flows.
- You can adjust your Number of jobs to as many processing cores as your host has. Then click OK.
- A large status window will appear. When that disappears, you can continue to monitor the status in the upper right corner of the Vivado cockpit.
- When bitstream generation is completed, click OK to Open Implemented Design.
Now that we’ve created an embedded system, we must make this platform available to the Vitis Software Development Kit (SDK). This is done by exporting the hardware platform.
- In the Vivado tool, select File > Export > Export Hardware.
- In the Export Hardware Platform dialog, click Next >
- Select the radio button for Include bitstream, and then click Next >
- Click Next > again.
- Click Finish
- We will now explore what you have created. In a file explorer, browse to your project directory.
You will notice seven directories and two files here. The.xpr file is your Vivado Project File and can be used to re-launch your project when you come back to work on it some more.
The.cache,.gen,.hw,.ip_user_files,.runs,.sim, and.srcs directories contain everything related to the hardware design, including the block design source, wrapper HDL, and synthesis/implementation results.
The XSA file is the result of the Export Hardware operation. Everything required for Vitis to import the hardware platform is contained inside this one file. A hardware engineer looking to share the design with the software team could provide this one file. This provides a very compact and portable method to send a ZU+ Hardware Platform to a colleague.
The next tutorial will show you how to open Vitis, import a hardware platform, and run Hello World. Vivado may be closed at this time.
Be sure to go to the next Tutorial!