Debugging CW305 Under Fault Using Digilent Digital Discovery

Introduction

While working with fault conditions such as clock glitch, voltage glitch on FPGAs, it is very difficult to diagnose what is going wrong inside and the reason behind it. There are multiple possibilities that can cause corruption under fault such as metastability, pipeline misalignment or any kind of hazard. An independent scope can make the observability higher for the tester in case we want to diagnose what actually is going wrong. Instead of fancy high price devices, we can use digilent digital discovery to probe in real time for debugging, validation and diagnostics.

Software

First install Waveform from here: My Products | Digilent

After you install and connect the device, you make sure select appropriate pins for probing. In waveform, go to Logic, select "click to add channels":

Then select pin 24-27 (or others if you need)

Then connect these pins with I/O pins of CW305.

Hardware

In this tutorial, we will run our test design in Chipwhisperer CW305 and we will run this under clock glitch. I'll not provide too much detail about the IP but it is fault sensitive and my produce incorrect intermediate values under fault. To see whether an intermediate value is corrupted, we'll be using Digitlent Digital Discovery. Our target is a 4 bit number but you can change it according to your necessity. We'll be using pin 24-27 of Digital Discovery to probe.

Now connect these pins to the desired pins of CW305, in this case pin B12, A13, B15, C11. You have set the correct constraints for these pins in Vivado project where you synthesize the design. Inside the vivado project on the top module, make sure you define the debug ports and connect those ports as follows:

`output wire  [3:0]                   debug,`
assign debug = aes_pt[3:0];                                                                            

Change the signals according to your necessity.

RunningDebugging

After connecting necessary pins from Digital Discovery to CW305, you can hit run in waveform and you'll be able to see the values you are trying to observe (that you have selected in the verilog design). Following is the output of my design under no fault:

Now if I inject fault using clock glitch, the intermediate values changes to this:

This is how we can increase observability for a design under fault without a fancy high end logic analyzer.